hardware.h 18 KB

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  1. /*
  2. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  3. *
  4. * Based on:
  5. *
  6. * -------------------------------------------------------------------------
  7. *
  8. * linux/include/asm-arm/arch-davinci/hardware.h
  9. *
  10. * Copyright (C) 2006 Texas Instruments.
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  18. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  20. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  23. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27. *
  28. * You should have received a copy of the GNU General Public License along
  29. * with this program; if not, write to the Free Software Foundation, Inc.,
  30. * 675 Mass Ave, Cambridge, MA 02139, USA.
  31. *
  32. */
  33. #ifndef __ASM_ARCH_HARDWARE_H
  34. #define __ASM_ARCH_HARDWARE_H
  35. #include <config.h>
  36. #include <asm/sizes.h>
  37. #define REG(addr) (*(volatile unsigned int *)(addr))
  38. #define REG_P(addr) ((volatile unsigned int *)(addr))
  39. typedef volatile unsigned int dv_reg;
  40. typedef volatile unsigned int * dv_reg_p;
  41. /*
  42. * Base register addresses
  43. *
  44. * NOTE: some of these DM6446-specific addresses DO NOT WORK
  45. * on other DaVinci chips. Double check them before you try
  46. * using the addresses ... or PSC module identifiers, etc.
  47. */
  48. #ifndef CONFIG_SOC_DA8XX
  49. #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
  50. #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
  51. #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
  52. #define DAVINCI_UART0_BASE (0x01c20000)
  53. #define DAVINCI_UART1_BASE (0x01c20400)
  54. #define DAVINCI_TIMER3_BASE (0x01c20800)
  55. #define DAVINCI_I2C_BASE (0x01c21000)
  56. #define DAVINCI_TIMER0_BASE (0x01c21400)
  57. #define DAVINCI_TIMER1_BASE (0x01c21800)
  58. #define DAVINCI_WDOG_BASE (0x01c21c00)
  59. #define DAVINCI_PWM0_BASE (0x01c22000)
  60. #define DAVINCI_PWM1_BASE (0x01c22400)
  61. #define DAVINCI_PWM2_BASE (0x01c22800)
  62. #define DAVINCI_TIMER4_BASE (0x01c23800)
  63. #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
  64. #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
  65. #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
  66. #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
  67. #define DAVINCI_ARM_INTC_BASE (0x01c48000)
  68. #define DAVINCI_USB_OTG_BASE (0x01c64000)
  69. #define DAVINCI_CFC_ATA_BASE (0x01c66000)
  70. #define DAVINCI_SPI_BASE (0x01c66800)
  71. #define DAVINCI_GPIO_BASE (0x01c67000)
  72. #define DAVINCI_VPSS_REGS_BASE (0x01c70000)
  73. #if !defined(CONFIG_SOC_DM646X)
  74. #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
  75. #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
  76. #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
  77. #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
  78. #endif
  79. #define DAVINCI_DDR_BASE (0x80000000)
  80. #ifdef CONFIG_SOC_DM644X
  81. #define DAVINCI_UART2_BASE 0x01c20800
  82. #define DAVINCI_UHPI_BASE 0x01c67800
  83. #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
  84. #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
  85. #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
  86. #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
  87. #define DAVINCI_IMCOP_BASE 0x01cc0000
  88. #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
  89. #define DAVINCI_VLYNQ_BASE 0x01e01000
  90. #define DAVINCI_ASP_BASE 0x01e02000
  91. #define DAVINCI_MMC_SD_BASE 0x01e10000
  92. #define DAVINCI_MS_BASE 0x01e20000
  93. #define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
  94. #elif defined(CONFIG_SOC_DM355)
  95. #define DAVINCI_MMC_SD1_BASE 0x01e00000
  96. #define DAVINCI_ASP0_BASE 0x01e02000
  97. #define DAVINCI_ASP1_BASE 0x01e04000
  98. #define DAVINCI_UART2_BASE 0x01e06000
  99. #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
  100. #define DAVINCI_MMC_SD0_BASE 0x01e11000
  101. #elif defined(CONFIG_SOC_DM365)
  102. #define DAVINCI_MMC_SD1_BASE 0x01d00000
  103. #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
  104. #define DAVINCI_MMC_SD0_BASE 0x01d11000
  105. #define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
  106. #define DAVINCI_SPI0_BASE 0x01c66000
  107. #define DAVINCI_SPI1_BASE 0x01c66800
  108. #elif defined(CONFIG_SOC_DM646X)
  109. #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
  110. #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
  111. #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
  112. #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
  113. #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
  114. #endif
  115. #else /* CONFIG_SOC_DA8XX */
  116. #define DAVINCI_UART0_BASE 0x01c42000
  117. #define DAVINCI_UART1_BASE 0x01d0c000
  118. #define DAVINCI_UART2_BASE 0x01d0d000
  119. #define DAVINCI_I2C0_BASE 0x01c22000
  120. #define DAVINCI_I2C1_BASE 0x01e28000
  121. #define DAVINCI_TIMER0_BASE 0x01c20000
  122. #define DAVINCI_TIMER1_BASE 0x01c21000
  123. #define DAVINCI_WDOG_BASE 0x01c21000
  124. #define DAVINCI_RTC_BASE 0x01c23000
  125. #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
  126. #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
  127. #define DAVINCI_PSC0_BASE 0x01c10000
  128. #define DAVINCI_PSC1_BASE 0x01e27000
  129. #define DAVINCI_SPI0_BASE 0x01c41000
  130. #define DAVINCI_USB_OTG_BASE 0x01e00000
  131. #define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
  132. 0x01e12000 : 0x01f0e000)
  133. #define DAVINCI_GPIO_BASE 0x01e26000
  134. #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
  135. #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
  136. #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
  137. #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
  138. #define DAVINCI_SYSCFG1_BASE 0x01e2c000
  139. #define DAVINCI_MMC_SD0_BASE 0x01c40000
  140. #define DAVINCI_MMC_SD1_BASE 0x01e1b000
  141. #define DAVINCI_TIMER2_BASE 0x01f0c000
  142. #define DAVINCI_TIMER3_BASE 0x01f0d000
  143. #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
  144. #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
  145. #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
  146. #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
  147. #define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
  148. #define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
  149. #define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
  150. #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
  151. #define DAVINCI_INTC_BASE 0xfffee000
  152. #define DAVINCI_BOOTCFG_BASE 0x01c14000
  153. #define DAVINCI_L3CBARAM_BASE 0x80000000
  154. #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
  155. #define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
  156. #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
  157. #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
  158. #define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
  159. #define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
  160. #define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
  161. #define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
  162. #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
  163. #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
  164. #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
  165. #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
  166. #endif /* CONFIG_SOC_DA8XX */
  167. /* Power and Sleep Controller (PSC) Domains */
  168. #define DAVINCI_GPSC_ARMDOMAIN 0
  169. #define DAVINCI_GPSC_DSPDOMAIN 1
  170. #ifndef CONFIG_SOC_DA8XX
  171. #define DAVINCI_LPSC_VPSSMSTR 0
  172. #define DAVINCI_LPSC_VPSSSLV 1
  173. #define DAVINCI_LPSC_TPCC 2
  174. #define DAVINCI_LPSC_TPTC0 3
  175. #define DAVINCI_LPSC_TPTC1 4
  176. #define DAVINCI_LPSC_EMAC 5
  177. #define DAVINCI_LPSC_EMAC_WRAPPER 6
  178. #define DAVINCI_LPSC_MDIO 7
  179. #define DAVINCI_LPSC_IEEE1394 8
  180. #define DAVINCI_LPSC_USB 9
  181. #define DAVINCI_LPSC_ATA 10
  182. #define DAVINCI_LPSC_VLYNQ 11
  183. #define DAVINCI_LPSC_UHPI 12
  184. #define DAVINCI_LPSC_DDR_EMIF 13
  185. #define DAVINCI_LPSC_AEMIF 14
  186. #define DAVINCI_LPSC_MMC_SD 15
  187. #define DAVINCI_LPSC_MEMSTICK 16
  188. #define DAVINCI_LPSC_McBSP 17
  189. #define DAVINCI_LPSC_I2C 18
  190. #define DAVINCI_LPSC_UART0 19
  191. #define DAVINCI_LPSC_UART1 20
  192. #define DAVINCI_LPSC_UART2 21
  193. #define DAVINCI_LPSC_SPI 22
  194. #define DAVINCI_LPSC_PWM0 23
  195. #define DAVINCI_LPSC_PWM1 24
  196. #define DAVINCI_LPSC_PWM2 25
  197. #define DAVINCI_LPSC_GPIO 26
  198. #define DAVINCI_LPSC_TIMER0 27
  199. #define DAVINCI_LPSC_TIMER1 28
  200. #define DAVINCI_LPSC_TIMER2 29
  201. #define DAVINCI_LPSC_SYSTEM_SUBSYS 30
  202. #define DAVINCI_LPSC_ARM 31
  203. #define DAVINCI_LPSC_SCR2 32
  204. #define DAVINCI_LPSC_SCR3 33
  205. #define DAVINCI_LPSC_SCR4 34
  206. #define DAVINCI_LPSC_CROSSBAR 35
  207. #define DAVINCI_LPSC_CFG27 36
  208. #define DAVINCI_LPSC_CFG3 37
  209. #define DAVINCI_LPSC_CFG5 38
  210. #define DAVINCI_LPSC_GEM 39
  211. #define DAVINCI_LPSC_IMCOP 40
  212. #define DAVINCI_DM646X_LPSC_EMAC 14
  213. #define DAVINCI_DM646X_LPSC_UART0 26
  214. #define DAVINCI_DM646X_LPSC_I2C 31
  215. #define DAVINCI_DM646X_LPSC_TIMER0 34
  216. #else /* CONFIG_SOC_DA8XX */
  217. #define DAVINCI_LPSC_TPCC 0
  218. #define DAVINCI_LPSC_TPTC0 1
  219. #define DAVINCI_LPSC_TPTC1 2
  220. #define DAVINCI_LPSC_AEMIF 3
  221. #define DAVINCI_LPSC_SPI0 4
  222. #define DAVINCI_LPSC_MMC_SD 5
  223. #define DAVINCI_LPSC_AINTC 6
  224. #define DAVINCI_LPSC_ARM_RAM_ROM 7
  225. #define DAVINCI_LPSC_SECCTL_KEYMGR 8
  226. #define DAVINCI_LPSC_UART0 9
  227. #define DAVINCI_LPSC_SCR0 10
  228. #define DAVINCI_LPSC_SCR1 11
  229. #define DAVINCI_LPSC_SCR2 12
  230. #define DAVINCI_LPSC_DMAX 13
  231. #define DAVINCI_LPSC_ARM 14
  232. #define DAVINCI_LPSC_GEM 15
  233. /* for LPSCs in PSC1, offset from 32 for differentiation */
  234. #define DAVINCI_LPSC_PSC1_BASE 32
  235. #define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
  236. #define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
  237. #define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
  238. #define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
  239. #define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
  240. #define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
  241. #define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
  242. #define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
  243. #define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
  244. #define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
  245. #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
  246. #define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
  247. #define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
  248. #define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
  249. #define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
  250. #define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
  251. /* DA830-specific peripherals */
  252. #define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
  253. #define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
  254. #define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
  255. #define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
  256. #define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
  257. #define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
  258. /* DA850-specific peripherals */
  259. #define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
  260. #define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
  261. #define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
  262. #define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
  263. #define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
  264. #define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
  265. #define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
  266. #define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
  267. #define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
  268. #define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
  269. #define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
  270. #define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
  271. #define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
  272. #define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
  273. #define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
  274. #endif /* CONFIG_SOC_DA8XX */
  275. void lpsc_on(unsigned int id);
  276. void lpsc_syncreset(unsigned int id);
  277. void dsp_on(void);
  278. void davinci_enable_uart0(void);
  279. void davinci_enable_emac(void);
  280. void davinci_enable_i2c(void);
  281. void davinci_errata_workarounds(void);
  282. #ifndef CONFIG_SOC_DA8XX
  283. /* Some PSC defines */
  284. #define PSC_CHP_SHRTSW (0x01c40038)
  285. #define PSC_GBLCTL (0x01c41010)
  286. #define PSC_EPCPR (0x01c41070)
  287. #define PSC_EPCCR (0x01c41078)
  288. #define PSC_PTCMD (0x01c41120)
  289. #define PSC_PTSTAT (0x01c41128)
  290. #define PSC_PDSTAT (0x01c41200)
  291. #define PSC_PDSTAT1 (0x01c41204)
  292. #define PSC_PDCTL (0x01c41300)
  293. #define PSC_PDCTL1 (0x01c41304)
  294. #define PSC_MDCTL_BASE (0x01c41a00)
  295. #define PSC_MDSTAT_BASE (0x01c41800)
  296. #define VDD3P3V_PWDN (0x01c40048)
  297. #define UART0_PWREMU_MGMT (0x01c20030)
  298. #define PSC_SILVER_BULLET (0x01c41a20)
  299. #else /* CONFIG_SOC_DA8XX */
  300. #define PSC_ENABLE 0x3
  301. #define PSC_DISABLE 0x2
  302. #define PSC_SYNCRESET 0x1
  303. #define PSC_SWRSTDISABLE 0x0
  304. #define PSC_PSC0_MODULE_ID_CNT 16
  305. #define PSC_PSC1_MODULE_ID_CNT 32
  306. struct davinci_psc_regs {
  307. dv_reg revid;
  308. dv_reg rsvd0[71];
  309. dv_reg ptcmd;
  310. dv_reg rsvd1;
  311. dv_reg ptstat;
  312. dv_reg rsvd2[437];
  313. union {
  314. struct {
  315. dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
  316. dv_reg rsvd3[112];
  317. dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
  318. } psc0;
  319. struct {
  320. dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
  321. dv_reg rsvd3[96];
  322. dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
  323. } psc1;
  324. };
  325. };
  326. #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
  327. #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
  328. #endif /* CONFIG_SOC_DA8XX */
  329. #define PSC_MDSTAT_STATE 0x3f
  330. #define PSC_MDCTL_NEXT 0x07
  331. #ifndef CONFIG_SOC_DA8XX
  332. /* Miscellania... */
  333. #define VBPR (0x20000020)
  334. /* NOTE: system control modules are *highly* chip-specific, both
  335. * as to register content (e.g. for muxing) and which registers exist.
  336. */
  337. #define PINMUX0 0x01c40000
  338. #define PINMUX1 0x01c40004
  339. #define PINMUX2 0x01c40008
  340. #define PINMUX3 0x01c4000c
  341. #define PINMUX4 0x01c40010
  342. #else /* CONFIG_SOC_DA8XX */
  343. struct davinci_pllc_regs {
  344. dv_reg revid;
  345. dv_reg rsvd1[56];
  346. dv_reg rstype;
  347. dv_reg rsvd2[6];
  348. dv_reg pllctl;
  349. dv_reg ocsel;
  350. dv_reg rsvd3[2];
  351. dv_reg pllm;
  352. dv_reg prediv;
  353. dv_reg plldiv1;
  354. dv_reg plldiv2;
  355. dv_reg plldiv3;
  356. dv_reg oscdiv;
  357. dv_reg postdiv;
  358. dv_reg rsvd4[3];
  359. dv_reg pllcmd;
  360. dv_reg pllstat;
  361. dv_reg alnctl;
  362. dv_reg dchange;
  363. dv_reg cken;
  364. dv_reg ckstat;
  365. dv_reg systat;
  366. dv_reg rsvd5[3];
  367. dv_reg plldiv4;
  368. dv_reg plldiv5;
  369. dv_reg plldiv6;
  370. dv_reg plldiv7;
  371. dv_reg rsvd6[32];
  372. dv_reg emucnt0;
  373. dv_reg emucnt1;
  374. };
  375. #define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
  376. #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
  377. #define DAVINCI_PLLC_DIV_MASK 0x1f
  378. #define ASYNC3 get_async3_src()
  379. #define PLL1_SYSCLK2 ((1 << 16) | 0x2)
  380. #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
  381. /* Clock IDs */
  382. enum davinci_clk_ids {
  383. DAVINCI_SPI0_CLKID = 2,
  384. DAVINCI_UART2_CLKID = 2,
  385. DAVINCI_MDIO_CLKID = 4,
  386. DAVINCI_ARM_CLKID = 6,
  387. DAVINCI_PLLM_CLKID = 0xff,
  388. DAVINCI_PLLC_CLKID = 0x100,
  389. DAVINCI_AUXCLK_CLKID = 0x101
  390. };
  391. int clk_get(enum davinci_clk_ids id);
  392. /* Boot config */
  393. struct davinci_syscfg_regs {
  394. dv_reg revid;
  395. dv_reg rsvd[13];
  396. dv_reg kick0;
  397. dv_reg kick1;
  398. dv_reg rsvd1[56];
  399. dv_reg pinmux[20];
  400. dv_reg suspsrc;
  401. dv_reg chipsig;
  402. dv_reg chipsig_clr;
  403. dv_reg cfgchip0;
  404. dv_reg cfgchip1;
  405. dv_reg cfgchip2;
  406. dv_reg cfgchip3;
  407. dv_reg cfgchip4;
  408. };
  409. #define davinci_syscfg_regs \
  410. ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
  411. /* Emulation suspend bits */
  412. #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
  413. #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
  414. #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
  415. #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
  416. #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
  417. #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
  418. struct davinci_syscfg1_regs {
  419. dv_reg vtpio_ctl;
  420. dv_reg ddr_slew;
  421. dv_reg deepsleep;
  422. dv_reg pupd_ena;
  423. dv_reg pupd_sel;
  424. dv_reg rxactive;
  425. dv_reg pwrdwn;
  426. };
  427. #define davinci_syscfg1_regs \
  428. ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
  429. #define DDR_SLEW_CMOSEN_BIT 4
  430. #define VTP_POWERDWN (1 << 6)
  431. #define VTP_LOCK (1 << 7)
  432. #define VTP_CLKRZ (1 << 13)
  433. #define VTP_READY (1 << 15)
  434. #define VTP_IOPWRDWN (1 << 14)
  435. /* Interrupt controller */
  436. struct davinci_aintc_regs {
  437. dv_reg revid;
  438. dv_reg cr;
  439. dv_reg dummy0[2];
  440. dv_reg ger;
  441. dv_reg dummy1[219];
  442. dv_reg ecr1;
  443. dv_reg ecr2;
  444. dv_reg ecr3;
  445. dv_reg dummy2[1117];
  446. dv_reg hier;
  447. };
  448. #define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
  449. struct davinci_uart_ctrl_regs {
  450. dv_reg revid1;
  451. dv_reg revid2;
  452. dv_reg pwremu_mgmt;
  453. dv_reg mdr;
  454. };
  455. #define DAVINCI_UART_CTRL_BASE 0x28
  456. #define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
  457. #define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
  458. #define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
  459. #define davinci_uart0_ctrl_regs \
  460. ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
  461. #define davinci_uart1_ctrl_regs \
  462. ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
  463. #define davinci_uart2_ctrl_regs \
  464. ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
  465. /* UART PWREMU_MGMT definitions */
  466. #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
  467. #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
  468. #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
  469. static inline int cpu_is_da830(void)
  470. {
  471. unsigned int jtag_id = REG(JTAG_ID_REG);
  472. unsigned short part_no = (jtag_id >> 12) & 0xffff;
  473. return ((part_no == 0xb7df) ? 1 : 0);
  474. }
  475. static inline int cpu_is_da850(void)
  476. {
  477. unsigned int jtag_id = REG(JTAG_ID_REG);
  478. unsigned short part_no = (jtag_id >> 12) & 0xffff;
  479. return ((part_no == 0xb7d1) ? 1 : 0);
  480. }
  481. static inline int get_async3_src(void)
  482. {
  483. return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
  484. PLL1_SYSCLK2 : 2;
  485. }
  486. #endif /* CONFIG_SOC_DA8XX */
  487. #if defined(CONFIG_SOC_DM365)
  488. #include <asm/arch/aintc_defs.h>
  489. #include <asm/arch/ddr2_defs.h>
  490. #include <asm/arch/emif_defs.h>
  491. #include <asm/arch/gpio.h>
  492. #include <asm/arch/pll_defs.h>
  493. #include <asm/arch/psc_defs.h>
  494. #include <asm/arch/syscfg_defs.h>
  495. #include <asm/arch/timer_defs.h>
  496. #endif
  497. #endif /* __ASM_ARCH_HARDWARE_H */