pcilib.h 12 KB

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  1. /****************************************************************************
  2. *
  3. * SciTech OS Portability Manager Library
  4. *
  5. * ========================================================================
  6. *
  7. * The contents of this file are subject to the SciTech MGL Public
  8. * License Version 1.0 (the "License"); you may not use this file
  9. * except in compliance with the License. You may obtain a copy of
  10. * the License at http://www.scitechsoft.com/mgl-license.txt
  11. *
  12. * Software distributed under the License is distributed on an
  13. * "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
  14. * implied. See the License for the specific language governing
  15. * rights and limitations under the License.
  16. *
  17. * The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
  18. *
  19. * The Initial Developer of the Original Code is SciTech Software, Inc.
  20. * All Rights Reserved.
  21. *
  22. * ========================================================================
  23. *
  24. * Language: ANSI C
  25. * Environment: Any
  26. *
  27. * Description: Header file for interface routines to the PCI bus.
  28. *
  29. ****************************************************************************/
  30. #ifndef __PCILIB_H
  31. #define __PCILIB_H
  32. #include "scitech.h"
  33. /*---------------------- Macros and type definitions ----------------------*/
  34. #pragma pack(1)
  35. /* Defines for PCIDeviceInfo.HeaderType */
  36. typedef enum {
  37. PCI_deviceType = 0x00,
  38. PCI_bridgeType = 0x01,
  39. PCI_cardBusBridgeType = 0x02,
  40. PCI_multiFunctionType = 0x80
  41. } PCIHeaderTypeFlags;
  42. /* Defines for PCIDeviceInfo.Command */
  43. typedef enum {
  44. PCI_enableIOSpace = 0x0001,
  45. PCI_enableMemorySpace = 0x0002,
  46. PCI_enableBusMaster = 0x0004,
  47. PCI_enableSpecialCylces = 0x0008,
  48. PCI_enableWriteAndInvalidate = 0x0010,
  49. PCI_enableVGACompatiblePalette = 0x0020,
  50. PCI_enableParity = 0x0040,
  51. PCI_enableWaitCycle = 0x0080,
  52. PCI_enableSerr = 0x0100,
  53. PCI_enableFastBackToBack = 0x0200
  54. } PCICommandFlags;
  55. /* Defines for PCIDeviceInfo.Status */
  56. typedef enum {
  57. PCI_statusCapabilitiesList = 0x0010,
  58. PCI_status66MhzCapable = 0x0020,
  59. PCI_statusUDFSupported = 0x0040,
  60. PCI_statusFastBackToBack = 0x0080,
  61. PCI_statusDataParityDetected = 0x0100,
  62. PCI_statusDevSel = 0x0600,
  63. PCI_statusSignaledTargetAbort = 0x0800,
  64. PCI_statusRecievedTargetAbort = 0x1000,
  65. PCI_statusRecievedMasterAbort = 0x2000,
  66. PCI_statusSignaledSystemError = 0x4000,
  67. PCI_statusDetectedParityError = 0x8000
  68. } PCIStatusFlags;
  69. /* PCI capability IDs */
  70. typedef enum {
  71. PCI_capsPowerManagement = 0x01,
  72. PCI_capsAGP = 0x02,
  73. PCI_capsMSI = 0x05
  74. } PCICapsType;
  75. /* PCI AGP rate definitions */
  76. typedef enum {
  77. PCI_AGPRate1X = 0x1,
  78. PCI_AGPRate2X = 0x2,
  79. PCI_AGPRate4X = 0x4
  80. } PCIAGPRateType;
  81. /* NOTE: We define all bitfield's as uint's, specifically so that the IBM
  82. * Visual Age C++ compiler does not complain. We need them to be
  83. * 32-bits wide, and this is the width of an unsigned integer, but
  84. * we can't use a ulong to make this explicit or we get errors.
  85. */
  86. /* Structure defining a PCI slot identifier */
  87. typedef union {
  88. struct {
  89. uint Zero:2;
  90. uint Register:6;
  91. uint Function:3;
  92. uint Device:5;
  93. uint Bus:8;
  94. uint Reserved:7;
  95. uint Enable:1;
  96. } p;
  97. ulong i;
  98. } PCIslot;
  99. /* Structure defining the regular (type 0) PCI configuration register
  100. * layout. We use this in a union below so we can describe all types of
  101. * PCI configuration spaces with a single structure.
  102. */
  103. typedef struct {
  104. ulong BaseAddress10;
  105. ulong BaseAddress14;
  106. ulong BaseAddress18;
  107. ulong BaseAddress1C;
  108. ulong BaseAddress20;
  109. ulong BaseAddress24;
  110. ulong CardbusCISPointer;
  111. ushort SubSystemVendorID;
  112. ushort SubSystemID;
  113. ulong ROMBaseAddress;
  114. uchar CapabilitiesPointer;
  115. uchar reserved1;
  116. uchar reserved2;
  117. uchar reserved3;
  118. ulong reserved4;
  119. uchar InterruptLine;
  120. uchar InterruptPin;
  121. uchar MinimumGrant;
  122. uchar MaximumLatency;
  123. /* These are not in the actual config space, but we enumerate them */
  124. ulong BaseAddress10Len;
  125. ulong BaseAddress14Len;
  126. ulong BaseAddress18Len;
  127. ulong BaseAddress1CLen;
  128. ulong BaseAddress20Len;
  129. ulong BaseAddress24Len;
  130. ulong ROMBaseAddressLen;
  131. } PCIType0Info;
  132. /* Structure defining PCI to PCI bridge (type 1) PCI configuration register
  133. * layout. We use this in a union below so we can describe all types of
  134. * PCI configuration spaces with a single structure.
  135. */
  136. typedef struct {
  137. ulong BaseAddress10;
  138. ulong BaseAddress14;
  139. uchar PrimaryBusNumber;
  140. uchar SecondayBusNumber;
  141. uchar SubordinateBusNumber;
  142. uchar SecondaryLatencyTimer;
  143. uchar IOBase;
  144. uchar IOLimit;
  145. ushort SecondaryStatus;
  146. ushort MemoryBase;
  147. ushort MemoryLimit;
  148. ushort PrefetchableMemoryBase;
  149. ushort PrefetchableMemoryLimit;
  150. ulong PrefetchableBaseHi;
  151. ulong PrefetchableLimitHi;
  152. ushort IOBaseHi;
  153. ushort IOLimitHi;
  154. uchar CapabilitiesPointer;
  155. uchar reserved1;
  156. uchar reserved2;
  157. uchar reserved3;
  158. ulong ROMBaseAddress;
  159. uchar InterruptLine;
  160. uchar InterruptPin;
  161. ushort BridgeControl;
  162. } PCIType1Info;
  163. /* PCI to CardBus bridge (type 2) configuration information */
  164. typedef struct {
  165. ulong SocketRegistersBaseAddress;
  166. uchar CapabilitiesPointer;
  167. uchar reserved1;
  168. ushort SecondaryStatus;
  169. uchar PrimaryBus;
  170. uchar SecondaryBus;
  171. uchar SubordinateBus;
  172. uchar SecondaryLatency;
  173. struct {
  174. ulong Base;
  175. ulong Limit;
  176. } Range[4];
  177. uchar InterruptLine;
  178. uchar InterruptPin;
  179. ushort BridgeControl;
  180. } PCIType2Info;
  181. /* Structure defining the PCI configuration space information for a
  182. * single PCI device on the PCI bus. We enumerate all this information
  183. * for all PCI devices on the bus.
  184. */
  185. typedef struct {
  186. ulong dwSize;
  187. PCIslot slot;
  188. ulong mech1;
  189. ushort VendorID;
  190. ushort DeviceID;
  191. ushort Command;
  192. ushort Status;
  193. uchar RevID;
  194. uchar Interface;
  195. uchar SubClass;
  196. uchar BaseClass;
  197. uchar CacheLineSize;
  198. uchar LatencyTimer;
  199. uchar HeaderType;
  200. uchar BIST;
  201. union {
  202. PCIType0Info type0;
  203. PCIType1Info type1;
  204. PCIType2Info type2;
  205. } u;
  206. } PCIDeviceInfo;
  207. /* PCI Capability header structure. All PCI capabilities have the
  208. * following header.
  209. *
  210. * capsID is used to identify the type of the structure as define above.
  211. *
  212. * next is the offset in PCI configuration space (0x40-0xFC) of the
  213. * next capability structure in the list, or 0x00 if there are no more
  214. * entries.
  215. */
  216. typedef struct {
  217. uchar capsID;
  218. uchar next;
  219. } PCICapsHeader;
  220. /* Structure defining the PCI AGP status register contents */
  221. typedef struct {
  222. uint rate:3;
  223. uint rsvd1:1;
  224. uint fastWrite:1;
  225. uint fourGB:1;
  226. uint rsvd2:3;
  227. uint sideBandAddressing:1;
  228. uint rsvd3:14;
  229. uint requestQueueDepthMaximum:8;
  230. } PCIAGPStatus;
  231. /* Structure defining the PCI AGP command register contents */
  232. typedef struct {
  233. uint rate:3;
  234. uint rsvd1:1;
  235. uint fastWriteEnable:1;
  236. uint fourGBEnable:1;
  237. uint rsvd2:2;
  238. uint AGPEnable:1;
  239. uint SBAEnable:1;
  240. uint rsvd3:14;
  241. uint requestQueueDepth:8;
  242. } PCIAGPCommand;
  243. /* AGP Capability structure */
  244. typedef struct {
  245. PCICapsHeader h;
  246. ushort majMin;
  247. PCIAGPStatus AGPStatus;
  248. PCIAGPCommand AGPCommand;
  249. } PCIAGPCapability;
  250. /* Structure for obtaining the PCI IRQ routing information */
  251. typedef struct {
  252. uchar bus;
  253. uchar device;
  254. uchar linkA;
  255. ushort mapA;
  256. uchar linkB;
  257. ushort mapB;
  258. uchar linkC;
  259. ushort mapC;
  260. uchar linkD;
  261. ushort mapD;
  262. uchar slot;
  263. uchar reserved;
  264. } PCIRouteInfo;
  265. typedef struct {
  266. ushort BufferSize;
  267. PCIRouteInfo *DataBuffer;
  268. } PCIRoutingOptionsBuffer;
  269. #define NUM_PCI_REG (sizeof(PCIDeviceInfo) / 4) - 10
  270. #define PCI_BRIDGE_CLASS 0x06
  271. #define PCI_HOST_BRIDGE_SUBCLASS 0x00
  272. #define PCI_EARLY_VGA_CLASS 0x00
  273. #define PCI_EARLY_VGA_SUBCLASS 0x01
  274. #define PCI_DISPLAY_CLASS 0x03
  275. #define PCI_DISPLAY_VGA_SUBCLASS 0x00
  276. #define PCI_DISPLAY_XGA_SUBCLASS 0x01
  277. #define PCI_DISPLAY_OTHER_SUBCLASS 0x80
  278. #define PCI_MM_CLASS 0x04
  279. #define PCI_AUDIO_SUBCLASS 0x01
  280. /* Macros to detect specific classes of devices */
  281. #define PCI_IS_3DLABS_NONVGA_CLASS(pci) \
  282. (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \
  283. && ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C))
  284. #define PCI_IS_DISPLAY_CLASS(pci) \
  285. (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \
  286. || ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \
  287. || ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \
  288. || PCI_IS_3DLABS_NONVGA_CLASS(pci))
  289. /* Function codes to pass to PCI_accessReg */
  290. #define PCI_READ_BYTE 0
  291. #define PCI_READ_WORD 1
  292. #define PCI_READ_DWORD 2
  293. #define PCI_WRITE_BYTE 3
  294. #define PCI_WRITE_WORD 4
  295. #define PCI_WRITE_DWORD 5
  296. /* Macros to read/write PCI registers. These assume a global PCI array
  297. * of device information.
  298. */
  299. #define PCI_readPCIRegB(index,device) \
  300. PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]])
  301. #define PCI_readPCIRegW(index,device) \
  302. PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]])
  303. #define PCI_readPCIRegL(index,device) \
  304. PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]])
  305. #define PCI_writePCIRegB(index,value,device) \
  306. PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]])
  307. #define PCI_writePCIRegW(index,value,device) \
  308. PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]])
  309. #define PCI_writePCIRegL(index,value,device) \
  310. PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]])
  311. #pragma pack()
  312. /*-------------------------- Function Prototypes --------------------------*/
  313. #ifdef __cplusplus
  314. extern "C" { /* Use "C" linkage when in C++ mode */
  315. #endif
  316. /* Function to determine the number of PCI devices in the system */
  317. int _ASMAPI PCI_getNumDevices(void);
  318. /* Function to enumerate all device on the PCI bus */
  319. int _ASMAPI PCI_enumerate(PCIDeviceInfo info[]);
  320. /* Function to access PCI configuration registers */
  321. ulong _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info);
  322. /* Function to get PCI IRQ routing options for a card */
  323. int _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer);
  324. /* Function to re-route the PCI IRQ setting for a device */
  325. ibool _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ);
  326. /* Function to generate a special cyle on the specified PCI bus */
  327. void _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData);
  328. /* Function to determine the size of a PCI base address register */
  329. ulong _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci);
  330. /* Function to read a block of PCI configuration space registers */
  331. void _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count);
  332. /* Function to write a block of PCI configuration space registers */
  333. void _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count);
  334. /* Function to return the 32-bit PCI BIOS entry point */
  335. ulong _ASMAPI PCIBIOS_getEntry(void);
  336. #ifdef __cplusplus
  337. } /* End of "C" linkage for C++ */
  338. #endif
  339. #endif /* __PCILIB_H */