usb_uhci.h 7.0 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Denis Peter, MPL AG Switzerland
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * Note: Part of this code has been derived from linux
  24. *
  25. */
  26. #ifndef _USB_UHCI_H_
  27. #define _USB_UHCI_H_
  28. #undef USB_UHCI_VEND_ID
  29. #define USB_UHCI_VEND_ID PCI_VENDOR_ID_VIA
  30. #undef USB_UHCI_DEV_ID
  31. #define USB_UHCI_DEV_ID 0x3038
  32. /* Command register */
  33. #define USBCMD 0
  34. #define USBCMD_RS 0x0001 /* Run/Stop */
  35. #define USBCMD_HCRESET 0x0002 /* Host reset */
  36. #define USBCMD_GRESET 0x0004 /* Global reset */
  37. #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
  38. #define USBCMD_FGR 0x0010 /* Force Global Resume */
  39. #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
  40. #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
  41. #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
  42. /* Status register */
  43. #define USBSTS 2
  44. #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
  45. #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
  46. #define USBSTS_RD 0x0004 /* Resume Detect */
  47. #define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
  48. #define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
  49. #define USBSTS_HCH 0x0020 /* HC Halted */
  50. /* Interrupt enable register */
  51. #define USBINTR 4
  52. #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
  53. #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
  54. #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
  55. #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
  56. #define USBFRNUM 6
  57. #define USBFLBASEADD 8
  58. #define USBSOF 12
  59. /* USB port status and control registers */
  60. #define USBPORTSC1 16
  61. #define USBPORTSC2 18
  62. #define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
  63. #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
  64. #define USBPORTSC_PE 0x0004 /* Port Enable */
  65. #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
  66. #define USBPORTSC_LS 0x0030 /* Line Status */
  67. #define USBPORTSC_RD 0x0040 /* Resume Detect */
  68. #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
  69. #define USBPORTSC_PR 0x0200 /* Port Reset */
  70. #define USBPORTSC_SUSP 0x1000 /* Suspend */
  71. /* Legacy support register */
  72. #define USBLEGSUP 0xc0
  73. #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
  74. #define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
  75. #define UHCI_PID 0xff /* PID MASK */
  76. #define UHCI_PTR_BITS 0x000F
  77. #define UHCI_PTR_TERM 0x0001
  78. #define UHCI_PTR_QH 0x0002
  79. #define UHCI_PTR_DEPTH 0x0004
  80. /* for TD <status>: */
  81. #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
  82. #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
  83. #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
  84. #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
  85. #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
  86. #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
  87. #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
  88. #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
  89. #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
  90. #define TD_CTRL_NAK (1 << 19) /* NAK Received */
  91. #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
  92. #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
  93. #define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
  94. #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
  95. TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
  96. #define TD_TOKEN_TOGGLE 19
  97. /* ------------------------------------------------------------------------------------
  98. Virtual Root HUB
  99. ------------------------------------------------------------------------------------ */
  100. /* destination of request */
  101. #define RH_INTERFACE 0x01
  102. #define RH_ENDPOINT 0x02
  103. #define RH_OTHER 0x03
  104. #define RH_CLASS 0x20
  105. #define RH_VENDOR 0x40
  106. /* Requests: bRequest << 8 | bmRequestType */
  107. #define RH_GET_STATUS 0x0080
  108. #define RH_CLEAR_FEATURE 0x0100
  109. #define RH_SET_FEATURE 0x0300
  110. #define RH_SET_ADDRESS 0x0500
  111. #define RH_GET_DESCRIPTOR 0x0680
  112. #define RH_SET_DESCRIPTOR 0x0700
  113. #define RH_GET_CONFIGURATION 0x0880
  114. #define RH_SET_CONFIGURATION 0x0900
  115. #define RH_GET_STATE 0x0280
  116. #define RH_GET_INTERFACE 0x0A80
  117. #define RH_SET_INTERFACE 0x0B00
  118. #define RH_SYNC_FRAME 0x0C80
  119. /* Our Vendor Specific Request */
  120. #define RH_SET_EP 0x2000
  121. /* Hub port features */
  122. #define RH_PORT_CONNECTION 0x00
  123. #define RH_PORT_ENABLE 0x01
  124. #define RH_PORT_SUSPEND 0x02
  125. #define RH_PORT_OVER_CURRENT 0x03
  126. #define RH_PORT_RESET 0x04
  127. #define RH_PORT_POWER 0x08
  128. #define RH_PORT_LOW_SPEED 0x09
  129. #define RH_C_PORT_CONNECTION 0x10
  130. #define RH_C_PORT_ENABLE 0x11
  131. #define RH_C_PORT_SUSPEND 0x12
  132. #define RH_C_PORT_OVER_CURRENT 0x13
  133. #define RH_C_PORT_RESET 0x14
  134. /* Hub features */
  135. #define RH_C_HUB_LOCAL_POWER 0x00
  136. #define RH_C_HUB_OVER_CURRENT 0x01
  137. #define RH_DEVICE_REMOTE_WAKEUP 0x00
  138. #define RH_ENDPOINT_STALL 0x01
  139. /* Our Vendor Specific feature */
  140. #define RH_REMOVE_EP 0x00
  141. #define RH_ACK 0x01
  142. #define RH_REQ_ERR -1
  143. #define RH_NACK 0x00
  144. /* Transfer descriptor structure */
  145. typedef struct {
  146. unsigned long link; /* next td/qh (LE)*/
  147. unsigned long status; /* status of the td */
  148. unsigned long info; /* Max Lenght / Endpoint / device address and PID */
  149. unsigned long buffer; /* pointer to data buffer (LE) */
  150. unsigned long dev_ptr; /* pointer to the assigned device (BE) */
  151. unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
  152. } uhci_td_t, *puhci_td_t;
  153. /* Queue Header structure */
  154. typedef struct {
  155. unsigned long head; /* Next QH (LE)*/
  156. unsigned long element; /* Queue element pointer (LE) */
  157. unsigned long res[5]; /* reserved */
  158. unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
  159. } uhci_qh_t, *puhci_qh_t;
  160. struct virt_root_hub {
  161. int devnum; /* Address of Root Hub endpoint */
  162. int numports; /* number of ports */
  163. int c_p_r[8]; /* C_PORT_RESET */
  164. };
  165. #endif /* _USB_UHCI_H_ */