board_asm_init.S 2.6 KB

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  1. #include "macros.h"
  2. #define GLOBALINFO0 0x50
  3. #define GLOBALINFO0_BO (1<<7)
  4. #define GLOBALINFO2_B1ARBITER (1<<6)
  5. #define HBUSACR0 0x5c
  6. #define HBUSACR2_BURST (1<<0)
  7. #define HBUSACR2_LAT (1<<1)
  8. #define RECEIVER_HOLDING 0
  9. #define TRANSMITTER_HOLDING 0
  10. #define INTERRUPT_ENABLE 1
  11. #define INTERRUPT_STATUS 2
  12. #define FIFO_CONTROL 2
  13. #define LINE_CONTROL 3
  14. #define MODEM_CONTROL 4
  15. #define LINE_STATUS 5
  16. #define MODEM_STATUS 6
  17. #define SCRATCH_PAD 7
  18. #define DIVISOR_LATCH_LSB 0
  19. #define DIVISOR_LATCH_MSB 1
  20. #define PRESCALER_DIVISION 5
  21. #define UART(x) (0x3f8+(x))
  22. #define GLOBALINFO0 0x50
  23. #define GLOBALINFO0_BO (1<<7)
  24. #define GLOBALINFO2_B1ARBITER (1<<6)
  25. #define HBUSACR0 0x5c
  26. #define HBUSACR2_BURST (1<<0)
  27. #define HBUSACR2_LAT (1<<1)
  28. #define SUPERIO_1 ((7 << 3) | (0))
  29. #define SUPERIO_2 ((7 << 3) | (1))
  30. .globl board_asm_init
  31. board_asm_init:
  32. mflr r29
  33. /* Set 'Must-set' register */
  34. li r3, 0
  35. li r4, 0
  36. li r5, 0x5e
  37. bl pci_read_cfg_byte
  38. ori r3, r3, (1<<1)
  39. xori r6, r3, (1<<1)
  40. li r3, 0
  41. bl pci_write_cfg_byte
  42. li r3, 0
  43. li r5, 0x52
  44. bl pci_read_cfg_byte
  45. ori r6, r3, (1<<6)
  46. li r3, 0
  47. bl pci_write_cfg_byte
  48. li r3, 0
  49. li r4, 0x08
  50. li r5, 0xd2
  51. bl pci_read_cfg_byte
  52. ori r6, r3, (1<<2)
  53. li r3, 0
  54. bl pci_write_cfg_byte
  55. /* Do PCI reset */
  56. /* li r3, 0
  57. li r4, 0x38
  58. li r5, 0x47
  59. bl pci_read_cfg_byte
  60. ori r6, r3, 0x01
  61. li r3, 0
  62. li r4, 0x38
  63. li r5, 0x47
  64. bl pci_write_cfg_byte*/
  65. /* Enable NVRAM for environment */
  66. li r3, 0
  67. li r4, 0
  68. li r5, 0x56
  69. li r6, 0x0B
  70. bl pci_write_cfg_byte
  71. /* Init Super-I/O chips */
  72. siowb 0x40, 0x08
  73. siowb 0x41, 0x01
  74. siowb 0x45, 0x80
  75. siowb 0x46, 0x60
  76. siowb 0x47, 0x20
  77. siowb 0x48, 0x01
  78. siowb 0x4a, 0xc4
  79. siowb 0x50, 0x0e
  80. siowb 0x51, 0x76
  81. siowb 0x52, 0x34
  82. siowb 0x54, 0x00
  83. siowb 0x55, 0x90
  84. siowb 0x56, 0x99
  85. siowb 0x57, 0x90
  86. siowb 0x85, 0x01
  87. /* Enable configuration mode for SuperIO */
  88. li r3, 0
  89. li r4, (7<<3)
  90. li r5, 0x85
  91. bl pci_read_cfg_byte
  92. ori r6, r3, 0x02
  93. mr r31, r6
  94. li r3,0
  95. bl pci_write_cfg_byte
  96. /* COM1 as 3f8 */
  97. outb 0x3f0, 0xe7
  98. outb 0x3f1, 0xfe
  99. /* COM2 as 2f8 */
  100. outb 0x3f0, 0xe8
  101. outb 0x3f1, 0xeb
  102. /* Enable */
  103. outb 0x3f0, 0xe2
  104. inb r3, 0x3f1
  105. ori r3, r3, 0x0c
  106. outb 0x3f0, 0xe2
  107. outbr 0x3f1, r3
  108. /* Disable configuration mode */
  109. li r3, 0
  110. li r4, (7<<3)
  111. li r5, 0x85
  112. mr r6, r31
  113. bl pci_write_cfg_byte
  114. /* Set line control */
  115. outb UART(LINE_CONTROL), 0x83
  116. outb UART(DIVISOR_LATCH_LSB), 0x0c
  117. outb UART(DIVISOR_LATCH_MSB), 0x00
  118. outb UART(LINE_CONTROL), 0x3
  119. mtlr r29
  120. blr
  121. .globl new_reset
  122. .globl new_reset_end
  123. new_reset:
  124. li r0, 0x100
  125. oris r0, r0, 0xFFF0
  126. mtlr r0
  127. blr
  128. new_reset_end: