articiaS.h 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142
  1. #ifndef ARTICIAS_H
  2. #define ARTICIAS_H
  3. #include "short_types.h"
  4. #include <common.h>
  5. #define REG_GROUP 0xF0
  6. /* ArticiaS registers */
  7. #define GLOBALINFO0 0x50
  8. #define GLOBALINFO1 0x51
  9. #define GLOBALINFO2 0x52
  10. #define GLOBALINFO3 0x53
  11. #define GLOBALCTL0 0x54
  12. #define GLOBALCTL1 0x55
  13. #define NVRAMCTL 0x56
  14. #define PCI1ACR0 0x58
  15. #define PCI1ACR1 0x59
  16. #define PCI1ACR2 0x5a
  17. #define PCI1ACR3 0x5b
  18. #define HBUSACR0 0x5c
  19. #define HBUSACR1 0x5d
  20. #define HBUSACR2 0x5e
  21. #define HBUSACR3 0x5f
  22. #define HOSTINT0 0x68
  23. #define HOSTINT1 0x69
  24. #define HOSTINT2 0x6a
  25. #define HOSTINT3 0x6b
  26. #define HOSTRBCR 0x70
  27. #define XDBCR 0x74
  28. #define LBSBCR2 0xd2
  29. /* Memory controller */
  30. #define DIMM0_B0_SCR0 0x90
  31. #define DIMM0_B1_SCR0 0x94
  32. #define DIMM1_B2_SCR0 0x98
  33. #define DIMM1_B3_SCR0 0x9c
  34. #define DIMM2_B4_SCR0 0xa0
  35. #define DIMM2_B5_SCR0 0xa4
  36. #define DIMM3_B6_SCR0 0xa8
  37. #define DIMM3_B7_SCR0 0xac
  38. #define DIMM0_TCR0 0xb0
  39. #define DIMM1_TCR0 0xb2
  40. #define DIMM2_TCR0 0xb4
  41. #define DIMM3_TCR0 0xb6
  42. #define DRAM_REFRESH0 0xb8
  43. #define DRAM_GCR0 0xc0
  44. #define DRAM_PCR0 0xc6
  45. #define DRAM_ECC0 0xc4
  46. #define SRAM_CR 0xc8
  47. #define DRAM_RAS_CTL0 0xcc
  48. #define DRAM_RAS_CTL1 0xcd
  49. /* Bits for REG_GROUP */
  50. #define REG_GROUP_MULTI (1<<1)
  51. #define REG_GROUP_SPECIAL (1<<3)
  52. #define REG_GROUP_DIAG (0x1<<4)
  53. #define REG_GROUP_POWER (0x2<<4)
  54. #define GLOBALINFO0_BO (1<<7)
  55. #define GLOBALINFO2_B1ARBITER (1<<6)
  56. #define HBUSACR0_CPUAPC (1<<0)
  57. #define HBUSACR0_NUMREQ_2 (0<<1)
  58. #define HBUSACR0_NUMREQ_3 (1<<1)
  59. #define HBUSACR0_NUMREQ_4 (2<<1)
  60. #define HBUSACR0_NUMREQ_MASK (7<<1)
  61. #define HBUSACR0_RAW (1<<6)
  62. #define HBUSACR0_WAIT (1<<7)
  63. #define HBUSACR0_RESERVED (0x30)
  64. #define HBUSACR2_BURST (1<<0)
  65. #define HBUSACR2_LAT (1<<1)
  66. #define HBUSACR3_LMWC_SM (1<<0)
  67. #define HBUSACR3_LMWC_PCI1 (1<<1)
  68. #define HBUSACR3_LMWC_PCI0 (1<<2)
  69. #define HBUSACR3_PMWC_PCI1 (1<<3)
  70. #define HBUSACR3_PMWC_PCI0 (1<<4)
  71. #define HBUSACR3_FKH (1<<5)
  72. #define HBUSACR3_92H_EN (1<<6)
  73. #define HBUSACR3_60H_64H_EN (1<<7)
  74. #define HOSTRBCR_PREFETCH (1<<4)
  75. #define XDBCR_HWTOXD (1<<0)
  76. #define XDBCR_KBTOXD (1<<1)
  77. #define XDBCR_RTCTOXD (1<<2)
  78. #define XDBCR_SCALE_1_1 (0x0<<3)
  79. #define XDBCR_SCALE_2_2 (0x1<<3)
  80. #define XDBCR_SCALE_3_2 (0x2<<3)
  81. #define XDBCR_SCALE_4_4 (0x3<<3)
  82. #define XDBCR_SCALE_5_8 (0x4<<3)
  83. #define XDBCR_SCALE_6_8 (0x5<<3)
  84. #define XDBCR_SCALE_8_8 (0x6<<3)
  85. #define XDBCR_SCALE_0_16 (0x7<<3)
  86. #define XDBCR_XDPROM (1<<7)
  87. #define LBSBCR2_1_RWAC (1<<2)
  88. /* PCI controller */
  89. #define ARTICIAS_PCI_CFGADDR 0xfec00cf8
  90. #define ARTICIAS_PCI_CFGDATA 0xfee00cfc
  91. #define ARTICIAS_PCI_BUS 0x80000000
  92. #define ARTICIAS_PCI_MAXSIZE 0x7cffffff
  93. #define ARTICIAS_PCI_PHYS 0x80000000
  94. #define ARTICIAS_SYS_BUS 0x00000000
  95. #define ARTICIAS_SYS_MAXSIZE 0x7fffffff
  96. #define ARTICIAS_SYS_PHYS 0x00000000
  97. #define ARTICIAS_PCIIO_BUS 0x00800000
  98. #define ARTICIAS_PCIIO_MAXSIZE 0x003fffff
  99. #define ARTICIAS_PCIIO_PHYS 0xfe800000
  100. #define ARTICIAS_ISAIO_BUS 0x00002000
  101. #define ARTICIAS_ISAIO_MAXSIZE 0x0000d000
  102. #define ARTICIAS_ISAIO_PHYS 0xfe002000
  103. /* Prototypes */
  104. long articiaS_ram_init(void);
  105. void articiaS_pci_init(void);
  106. #endif