articiaS.c 18 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <pci.h>
  25. #include <asm/processor.h>
  26. #include "memio.h"
  27. #include "articiaS.h"
  28. #include "smbus.h"
  29. #include "via686.h"
  30. #undef DEBUG
  31. struct dimm_bank {
  32. uint8 used; /* Bank is populated */
  33. uint32 rows; /* Number of row addresses */
  34. uint32 columns; /* Number of column addresses */
  35. uint8 registered; /* SIMM is registered */
  36. uint8 ecc; /* SIMM has ecc */
  37. uint8 burst_len; /* Supported burst lengths */
  38. uint32 cas_lat; /* Supported CAS latencies */
  39. uint32 cas_used; /* CAS to use (not set by user) */
  40. uint32 trcd; /* RAS to CAS latency */
  41. uint32 trp; /* Precharge latency */
  42. uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */
  43. uint32 tclk_2hi; /* SDRAM second highest CAS latency */
  44. uint32 size; /* Size of bank in bytes */
  45. uint8 auto_refresh; /* Module supports auto refresh */
  46. uint32 refresh_time; /* Refresh time (in ns) */
  47. };
  48. /*
  49. ** Based in part on the evb64260 code
  50. */
  51. /*
  52. * translate ns.ns/10 coding of SPD timing values
  53. * into 10 ps unit values
  54. */
  55. static inline unsigned short NS10to10PS (unsigned char spd_byte)
  56. {
  57. unsigned short ns, ns10;
  58. /* isolate upper nibble */
  59. ns = (spd_byte >> 4) & 0x0F;
  60. /* isolate lower nibble */
  61. ns10 = (spd_byte & 0x0F);
  62. return (ns * 100 + ns10 * 10);
  63. }
  64. /*
  65. * translate ns coding of SPD timing values
  66. * into 10 ps unit values
  67. */
  68. static inline unsigned short NSto10PS (unsigned char spd_byte)
  69. {
  70. return (spd_byte * 100);
  71. }
  72. long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
  73. {
  74. DECLARE_GLOBAL_DATA_PTR;
  75. int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
  76. uint32 busclock = gd->bus_clk;
  77. uint32 memclock = busclock;
  78. uint32 tmemclock = 1000000000 / (memclock / 100);
  79. uint32 datawidth;
  80. if (sm_get_data (rom, dimm_address) == 0) {
  81. /* Nothing in slot, make both banks empty */
  82. debug ("Slot %d: vacant\n", dimmNum);
  83. banks[0].used = 0;
  84. banks[1].used = 0;
  85. return 0;
  86. }
  87. if (rom[2] != 0x04) {
  88. debug ("Slot %d: No SDRAM\n", dimmNum);
  89. banks[0].used = 0;
  90. banks[1].used = 0;
  91. return 0;
  92. }
  93. /* Determine number of banks/rows */
  94. if (rom[5] == 1) {
  95. banks[0].used = 1;
  96. banks[1].used = 0;
  97. } else {
  98. banks[0].used = 1;
  99. banks[1].used = 1;
  100. }
  101. /* Determine number of row addresses */
  102. if (rom[3] & 0xf0) {
  103. /* Different banks sizes */
  104. banks[0].rows = rom[3] & 0x0f;
  105. banks[1].rows = (rom[3] & 0xf0) >> 4;
  106. } else {
  107. /* Equal sized banks */
  108. banks[0].rows = rom[3] & 0x0f;
  109. banks[1].rows = banks[0].rows;
  110. }
  111. /* Determine number of column addresses */
  112. if (rom[4] & 0xf0) {
  113. /* Different bank sizes */
  114. banks[0].columns = rom[4] & 0x0f;
  115. banks[1].columns = (rom[4] & 0xf0) >> 4;
  116. } else {
  117. banks[0].columns = rom[4] & 0x0f;
  118. banks[1].columns = banks[0].columns;
  119. }
  120. /* Check Jedec revision, and modify row/column accordingly */
  121. if (rom[62] > 0x10) {
  122. if (banks[0].rows <= 3)
  123. banks[0].rows += 15;
  124. if (banks[1].rows <= 3)
  125. banks[1].rows += 15;
  126. if (banks[0].columns <= 3)
  127. banks[0].columns += 15;
  128. if (banks[0].columns <= 3)
  129. banks[0].columns += 15;
  130. }
  131. /* Check registered/unregisterd */
  132. if (rom[21] & 0x12) {
  133. banks[0].registered = 1;
  134. banks[1].registered = 1;
  135. } else {
  136. banks[0].registered = 0;
  137. banks[1].registered = 0;
  138. }
  139. #ifdef CONFIG_ECC
  140. /* Check parity/ECC */
  141. banks[0].ecc = (rom[11] == 0x02);
  142. banks[1].ecc = (rom[11] == 0x02);
  143. #endif
  144. /* Find burst lengths supported */
  145. banks[0].burst_len = rom[16] & 0x8f;
  146. banks[1].burst_len = rom[16] & 0x8f;
  147. /* Find possible cas latencies */
  148. banks[0].cas_lat = rom[18] & 0x7F;
  149. banks[1].cas_lat = rom[18] & 0x7F;
  150. /* RAS/CAS latency */
  151. banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
  152. banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
  153. /* Precharge latency */
  154. banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
  155. banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
  156. /* highest CAS latency */
  157. banks[0].tclk_hi = NS10to10PS (rom[9]);
  158. banks[1].tclk_hi = NS10to10PS (rom[9]);
  159. /* second highest CAS latency */
  160. banks[0].tclk_2hi = NS10to10PS (rom[23]);
  161. banks[1].tclk_2hi = NS10to10PS (rom[23]);
  162. /* bank sizes */
  163. datawidth = rom[13] & 0x7f;
  164. banks[0].size =
  165. (1L << (banks[0].rows + banks[0].columns)) *
  166. /* FIXME datawidth */ 8 * rom[17];
  167. if (rom[13] & 0x80)
  168. banks[1].size = 2 * banks[0].size;
  169. else
  170. banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
  171. /* FIXME datawidth */ 8 * rom[17];
  172. /* Refresh */
  173. if (rom[12] & 0x80) {
  174. banks[0].auto_refresh = 1;
  175. banks[1].auto_refresh = 1;
  176. } else {
  177. banks[0].auto_refresh = 0;
  178. banks[1].auto_refresh = 0;
  179. }
  180. switch (rom[12] & 0x7f) {
  181. case 0:
  182. banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
  183. banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
  184. break;
  185. case 1:
  186. banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
  187. banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
  188. break;
  189. case 2:
  190. banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
  191. banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
  192. break;
  193. case 3:
  194. banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
  195. banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
  196. break;
  197. case 4:
  198. banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
  199. banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
  200. break;
  201. case 5:
  202. banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
  203. banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
  204. break;
  205. default:
  206. banks[0].refresh_time = 0x100; /* Default of Articia S */
  207. banks[1].refresh_time = 0x100;
  208. break;
  209. }
  210. #ifdef DEBUG
  211. printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
  212. printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
  213. printf ("Number of row addresses: %ld\n", banks[0].rows);
  214. printf ("Number of coumns addresses: %ld\n", banks[0].columns);
  215. printf ("SIMM is %sregistered\n",
  216. banks[0].registered == 0 ? "not " : "");
  217. #ifdef CONFIG_ECC
  218. printf ("SIMM %s ECC\n",
  219. banks[0].ecc == 1 ? "supports" : "doesn't support");
  220. #endif
  221. printf ("Supported burst lenghts: %s %s %s %s %s\n",
  222. banks[0].burst_len & 0x08 ? "8" : " ",
  223. banks[0].burst_len & 0x04 ? "4" : " ",
  224. banks[0].burst_len & 0x02 ? "2" : " ",
  225. banks[0].burst_len & 0x01 ? "1" : " ",
  226. banks[0].burst_len & 0x80 ? "PAGE" : " ");
  227. printf ("Supported CAS latencies: %s %s %s\n",
  228. banks[0].cas_lat & 0x04 ? "CAS 3" : " ",
  229. banks[0].cas_lat & 0x02 ? "CAS 2" : " ",
  230. banks[0].cas_lat & 0x01 ? "CAS 1" : " ");
  231. printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
  232. printf ("Precharge latency: %ld\n", banks[0].trp);
  233. printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
  234. printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
  235. printf ("SDRAM data width: %ld\n", datawidth);
  236. printf ("Auto Refresh %ssupported\n",
  237. banks[0].auto_refresh ? "" : "not ");
  238. printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
  239. if (banks[0].used)
  240. printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
  241. if (banks[1].used)
  242. printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
  243. printf ("\n");
  244. #endif
  245. sm_term ();
  246. return 1;
  247. }
  248. void select_cas (struct dimm_bank *banks, uint8 fast)
  249. {
  250. if (!banks[0].used) {
  251. banks[0].cas_used = 0;
  252. banks[0].cas_used = 0;
  253. return;
  254. }
  255. if (fast) {
  256. /* Search for fast CAS */
  257. uint32 i;
  258. uint32 c = 0x01;
  259. for (i = 1; i < 5; i++) {
  260. if (banks[0].cas_lat & c) {
  261. banks[0].cas_used = i;
  262. banks[1].cas_used = i;
  263. debug ("Using CAS %d (fast)\n", i);
  264. return;
  265. }
  266. c <<= 1;
  267. }
  268. /* Default to CAS 3 */
  269. banks[0].cas_used = 3;
  270. banks[1].cas_used = 3;
  271. debug ("Using CAS 3 (fast)\n");
  272. return;
  273. } else {
  274. /* Search for slow cas */
  275. uint32 i;
  276. uint32 c = 0x08;
  277. for (i = 4; i > 1; i--) {
  278. if (banks[0].cas_lat & c) {
  279. banks[0].cas_used = i;
  280. banks[1].cas_used = i;
  281. debug ("Using CAS %d (slow)\n", i);
  282. return;
  283. }
  284. c >>= 1;
  285. }
  286. /* Default to CAS 3 */
  287. banks[0].cas_used = 3;
  288. banks[1].cas_used = 3;
  289. debug ("Using CAS 3 (slow)\n");
  290. return;
  291. }
  292. banks[0].cas_used = 3;
  293. banks[1].cas_used = 3;
  294. debug ("Using CAS 3\n");
  295. return;
  296. }
  297. uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
  298. {
  299. uint32 i;
  300. struct RowColumnSize {
  301. uint32 banks;
  302. uint32 rows;
  303. uint32 columns;
  304. uint32 size;
  305. uint32 register_value;
  306. };
  307. struct RowColumnSize rcs_map[] = {
  308. /* Sbk Radr Cadr MB Value */
  309. {1, 11, 8, 8, 0x00840f00},
  310. {1, 11, 9, 16, 0x00925f00},
  311. {1, 11, 10, 32, 0x00a64f00},
  312. {2, 12, 8, 32, 0x00c55f00},
  313. {2, 12, 9, 64, 0x00d66f00},
  314. {2, 12, 10, 128, 0x00e77f00},
  315. {2, 12, 11, 256, 0x00ff8f00},
  316. {2, 13, 11, 512, 0x00ff9f00},
  317. {0, 0, 0, 0, 0x00000000}
  318. };
  319. i = 0;
  320. while (rcs_map[i].banks != 0) {
  321. if (rows == rcs_map[i].rows
  322. && columns == rcs_map[i].columns
  323. && (size / 1024 / 1024) == rcs_map[i].size)
  324. return rcs_map[i].register_value;
  325. i++;
  326. }
  327. return 0;
  328. }
  329. uint32 burst_to_len (uint32 support)
  330. {
  331. if (support & 0x80)
  332. return 0x7;
  333. else if (support & 0x8)
  334. return 0x3;
  335. else if (support & 0x4)
  336. return 0x2;
  337. else if (support & 0x2)
  338. return 0x1;
  339. else if (support & 0x1)
  340. return 0x0;
  341. return 0;
  342. }
  343. long articiaS_ram_init (void)
  344. {
  345. DECLARE_GLOBAL_DATA_PTR;
  346. register uint32 i;
  347. register uint32 value1;
  348. register uint32 value2;
  349. uint8 rom[128];
  350. uint32 burst_len;
  351. uint32 burst_support;
  352. uint32 total_ram = 0;
  353. struct dimm_bank banks[4]; /* FIXME: Move to initram */
  354. uint32 busclock = gd->bus_clk;
  355. uint32 memclock = busclock;
  356. uint32 reg32;
  357. uint32 refresh_clocks;
  358. uint8 auto_refresh;
  359. memset (banks, 0, sizeof (struct dimm_bank) * 4);
  360. detect_sdram (rom, 0, &banks[0]);
  361. detect_sdram (rom, 1, &banks[2]);
  362. for (i = 0; i < 4; i++) {
  363. total_ram = total_ram + (banks[i].used * banks[i].size);
  364. }
  365. pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
  366. pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
  367. pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */
  368. pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
  369. pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */
  370. pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */
  371. /* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
  372. if (banks[0].used) {
  373. value1 = get_reg_setting (banks[0].used + banks[1].used,
  374. banks[0].rows, banks[0].columns,
  375. banks[0].size);
  376. } else {
  377. value1 = 0;
  378. }
  379. if (banks[1].used) {
  380. value2 = get_reg_setting (banks[0].used + banks[1].used,
  381. banks[1].rows, banks[1].columns,
  382. banks[1].size);
  383. } else {
  384. value2 = 0;
  385. }
  386. pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
  387. pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
  388. debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
  389. debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
  390. if (banks[2].used) {
  391. value1 = get_reg_setting (banks[2].used + banks[3].used,
  392. banks[2].rows, banks[2].columns,
  393. banks[2].size);
  394. } else {
  395. value1 = 0;
  396. }
  397. if (banks[3].used) {
  398. value2 = get_reg_setting (banks[2].used + banks[3].used,
  399. banks[3].rows, banks[3].columns,
  400. banks[3].size);
  401. } else {
  402. value2 = 0;
  403. }
  404. pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
  405. pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
  406. debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
  407. debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
  408. pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
  409. pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
  410. pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
  411. pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
  412. /* Determine timing */
  413. select_cas (&banks[0], 0);
  414. select_cas (&banks[2], 0);
  415. /* FIXME: What about write recovery */
  416. /* Auto refresh Precharge */
  417. #if 0
  418. reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
  419. /* Write recovery CAS Latency */
  420. (0x1 << 6) | (banks[0].cas_used << 4) |
  421. /* RAS/CAS latency */
  422. ((banks[0].trcd - 1) << 0);
  423. reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
  424. (0x1 << 6) | (banks[2].cas_used << 4) |
  425. ((banks[2].trcd - 1) << 0)) << 16;
  426. #else
  427. if (100000000 == gd->bus_clk)
  428. reg32 = 0x71737173;
  429. else
  430. reg32 = 0x69736973;
  431. #endif
  432. pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
  433. debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
  434. /* Write default in DIMM2/3 (not used on A1) */
  435. pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
  436. /* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
  437. reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
  438. reg32 &= 0xFF00FFFF;
  439. #if 0
  440. if (banks[0].used && banks[0].registered)
  441. reg32 |= 0x1 << 16;
  442. if (banks[2].used && banks[2].registered)
  443. reg32 |= 0x1 << 18;
  444. #else
  445. if (banks[0].registered || banks[2].registered)
  446. reg32 |= 0x55 << 16;
  447. #endif
  448. pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
  449. debug ("DRAM_GCR0 = 0x%08x\n", reg32);
  450. /* Determine refresh */
  451. refresh_clocks = 0xffffffff;
  452. auto_refresh = 1;
  453. for (i = 0; i < 4; i++) {
  454. if (banks[i].used) {
  455. if (banks[i].auto_refresh == 0)
  456. auto_refresh = 0;
  457. if (banks[i].refresh_time < refresh_clocks)
  458. refresh_clocks = banks[i].refresh_time;
  459. }
  460. }
  461. #if 1
  462. /* It seems this is suggested by the ArticiaS data book */
  463. if (100000000 == gd->bus_clk)
  464. refresh_clocks = 1561;
  465. else
  466. refresh_clocks = 2083;
  467. #endif
  468. debug ("Refresh set to %ld clocks, auto refresh %s\n",
  469. refresh_clocks, auto_refresh ? "on" : "off");
  470. pci_write_cfg_long (0, 0, DRAM_REFRESH0,
  471. (1 << 16) | (1 << 15) | (auto_refresh << 12) |
  472. (refresh_clocks));
  473. debug ("DRAM_REFRESH0 = 0x%08x\n",
  474. (1 << 16) | (1 << 15) | (auto_refresh << 12) |
  475. (refresh_clocks));
  476. /* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */
  477. /* Set mode registers */
  478. /* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
  479. /* Find a common burst len */
  480. burst_support = 0xff;
  481. if (banks[0].used)
  482. burst_support = banks[0].burst_len;
  483. if (banks[1].used)
  484. burst_support = banks[1].burst_len;
  485. if (banks[2].used)
  486. burst_support = banks[2].burst_len;
  487. if (banks[3].used)
  488. burst_support = banks[3].burst_len;
  489. /*
  490. ** Mode register:
  491. ** Bits Use
  492. ** 0-2 Burst len
  493. ** 3 Burst type (0 = sequential, 1 = interleave)
  494. ** 4-6 CAS latency
  495. ** 7-8 Operation mode (0 = default, all others invalid)
  496. ** 9 Write burst
  497. ** 10-11 Reserved
  498. **
  499. ** Mode register burst table:
  500. ** A2 A1 A0 lenght
  501. ** 0 0 0 1
  502. ** 0 0 1 2
  503. ** 0 1 0 4
  504. ** 0 1 1 8
  505. ** 1 0 0 invalid
  506. ** 1 0 1 invalid
  507. ** 1 1 0 invalid
  508. ** 1 1 1 page (only valid for non-interleaved)
  509. */
  510. burst_len = burst_to_len (burst_support);
  511. burst_len = 2; /* FIXME */
  512. if (banks[0].used) {
  513. pci_write_cfg_word (0, 0, DRAM_PCR0,
  514. 0x8000 | burst_len | (banks[0].cas_used << 4));
  515. debug ("Mode bank 0: 0x%08x\n",
  516. 0x8000 | burst_len | (banks[0].cas_used << 4));
  517. } else {
  518. /* Seems to be needed to disable the bank */
  519. pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
  520. }
  521. if (banks[1].used) {
  522. pci_write_cfg_word (0, 0, DRAM_PCR0,
  523. 0x9000 | burst_len | (banks[1].cas_used << 4));
  524. debug ("Mode bank 1: 0x%08x\n",
  525. 0x8000 | burst_len | (banks[1].cas_used << 4));
  526. } else {
  527. /* Seems to be needed to disable the bank */
  528. pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
  529. }
  530. if (banks[2].used) {
  531. pci_write_cfg_word (0, 0, DRAM_PCR0,
  532. 0xa000 | burst_len | (banks[2].cas_used << 4));
  533. debug ("Mode bank 2: 0x%08x\n",
  534. 0x8000 | burst_len | (banks[2].cas_used << 4));
  535. } else {
  536. /* Seems to be needed to disable the bank */
  537. pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
  538. }
  539. if (banks[3].used) {
  540. pci_write_cfg_word (0, 0, DRAM_PCR0,
  541. 0xb000 | burst_len | (banks[3].cas_used << 4));
  542. debug ("Mode bank 3: 0x%08x\n",
  543. 0x8000 | burst_len | (banks[3].cas_used << 4));
  544. } else {
  545. /* Seems to be needed to disable the bank */
  546. pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
  547. }
  548. pci_write_cfg_word (0, 0, 0xba, 0x00);
  549. return total_ram;
  550. }
  551. extern int drv_isa_kbd_init (void);
  552. int last_stage_init (void)
  553. {
  554. drv_isa_kbd_init ();
  555. return 0;
  556. }
  557. int overwrite_console (void)
  558. {
  559. return (0);
  560. }
  561. #define in_8 read_byte
  562. #define out_8 write_byte
  563. static __inline__ unsigned long get_msr (void)
  564. {
  565. unsigned long msr;
  566. asm volatile ("mfmsr %0":"=r" (msr):);
  567. return msr;
  568. }
  569. static __inline__ void set_msr (unsigned long msr)
  570. {
  571. asm volatile ("mtmsr %0"::"r" (msr));
  572. }
  573. int board_pre_init (void)
  574. {
  575. unsigned char c_value = 0;
  576. unsigned long msr;
  577. /* Basic init of PS/2 keyboard (needed for some reason)... */
  578. /* Ripped from John's code */
  579. while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
  580. out_8 ((unsigned char *) 0xfe000064, 0xaa);
  581. while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
  582. c_value = in_8 ((unsigned char *) 0xfe000060);
  583. while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
  584. out_8 ((unsigned char *) 0xfe000064, 0xab);
  585. while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
  586. c_value = in_8 ((unsigned char *) 0xfe000060);
  587. while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
  588. out_8 ((unsigned char *) 0xfe000064, 0xae);
  589. /* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
  590. /* c_value = in_8((unsigned char *)0xfe000060); */
  591. /* Enable FPU */
  592. msr = get_msr ();
  593. set_msr (msr | MSR_FP);
  594. via_calibrate_bus_freq ();
  595. return 0;
  596. }