elpt860.c 11 KB

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  1. /*
  2. **=====================================================================
  3. **
  4. ** Copyright (C) 2000, 2001, 2002, 2003
  5. ** The LEOX team <team@leox.org>, http://www.leox.org
  6. **
  7. ** LEOX.org is about the development of free hardware and software resources
  8. ** for system on chip.
  9. **
  10. ** Description: U-Boot port on the LEOX's ELPT860 CPU board
  11. ** ~~~~~~~~~~~
  12. **
  13. **=====================================================================
  14. **
  15. ** This program is free software; you can redistribute it and/or
  16. ** modify it under the terms of the GNU General Public License as
  17. ** published by the Free Software Foundation; either version 2 of
  18. ** the License, or (at your option) any later version.
  19. **
  20. ** This program is distributed in the hope that it will be useful,
  21. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. ** GNU General Public License for more details.
  24. **
  25. ** You should have received a copy of the GNU General Public License
  26. ** along with this program; if not, write to the Free Software
  27. ** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. ** MA 02111-1307 USA
  29. **
  30. **=====================================================================
  31. */
  32. /*
  33. ** Note 1: In this file, you have to provide the following functions:
  34. ** ------
  35. ** int board_pre_init(void)
  36. ** int checkboard(void)
  37. ** long int initdram(int board_type)
  38. ** called from 'board_init_f()' into 'common/board.c'
  39. **
  40. ** void reset_phy(void)
  41. ** called from 'board_init_r()' into 'common/board.c'
  42. */
  43. #include <common.h>
  44. #include <mpc8xx.h>
  45. /* ------------------------------------------------------------------------- */
  46. static long int dram_size (long int, long int *, long int);
  47. /* ------------------------------------------------------------------------- */
  48. #define _NOT_USED_ 0xFFFFFFFF
  49. const uint init_sdram_table[] =
  50. {
  51. /*
  52. * Single Read. (Offset 0 in UPMA RAM)
  53. */
  54. 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
  55. 0xFFFFFC04, /* last */
  56. /*
  57. * SDRAM Initialization (offset 5 in UPMA RAM)
  58. *
  59. * This is no UPM entry point. The following definition uses
  60. * the remaining space to establish an initialization
  61. * sequence, which is executed by a RUN command.
  62. *
  63. */
  64. 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
  65. /*
  66. * Burst Read. (Offset 8 in UPMA RAM)
  67. */
  68. 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  69. 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  70. 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
  71. 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
  72. /*
  73. * Single Write. (Offset 18 in UPMA RAM)
  74. */
  75. 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
  76. 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
  77. /*
  78. * Burst Write. (Offset 20 in UPMA RAM)
  79. */
  80. 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  81. 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
  82. 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
  83. 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
  84. };
  85. const uint sdram_table[] =
  86. {
  87. /*
  88. * Single Read. (Offset 0 in UPMA RAM)
  89. */
  90. 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
  91. 0xFF0FFC00, /* last */
  92. /*
  93. * SDRAM Initialization (offset 5 in UPMA RAM)
  94. *
  95. * This is no UPM entry point. The following definition uses
  96. * the remaining space to establish an initialization
  97. * sequence, which is executed by a RUN command.
  98. *
  99. */
  100. 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
  101. /*
  102. * Burst Read. (Offset 8 in UPMA RAM)
  103. */
  104. 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
  105. 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
  106. 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
  107. 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
  108. /*
  109. * Single Write. (Offset 18 in UPMA RAM)
  110. */
  111. 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
  112. 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
  113. _NOT_USED_,
  114. /*
  115. * Burst Write. (Offset 20 in UPMA RAM)
  116. */
  117. 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
  118. 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
  119. 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
  120. 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
  121. /*
  122. * Refresh (Offset 30 in UPMA RAM)
  123. */
  124. 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  125. 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
  126. 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
  127. /*
  128. * Exception. (Offset 3c in UPMA RAM)
  129. */
  130. 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
  131. };
  132. /* ------------------------------------------------------------------------- */
  133. #define CFG_PC4 0x0800
  134. #define CFG_DS1 CFG_PC4
  135. /*
  136. * Very early board init code (fpga boot, etc.)
  137. */
  138. int
  139. board_pre_init (void)
  140. {
  141. volatile immap_t *immr = (immap_t *) CFG_IMMR;
  142. /*
  143. * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
  144. */
  145. immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
  146. immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
  147. immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
  148. return ( 0 ); /* success */
  149. }
  150. /*
  151. * Check Board Identity:
  152. *
  153. * Test ELPT860 ID string
  154. *
  155. * Return 1 if no second DRAM bank, otherwise returns 0
  156. */
  157. int
  158. checkboard (void)
  159. {
  160. unsigned char *s = getenv("serial#");
  161. if ( !s || strncmp(s, "ELPT860", 7) )
  162. printf ("### No HW ID - assuming ELPT860\n");
  163. return ( 0 ); /* success */
  164. }
  165. /* ------------------------------------------------------------------------- */
  166. long int
  167. initdram (int board_type)
  168. {
  169. volatile immap_t *immap = (immap_t *)CFG_IMMR;
  170. volatile memctl8xx_t *memctl = &immap->im_memctl;
  171. long int size8, size9;
  172. long int size_b0 = 0;
  173. /*
  174. * This sequence initializes SDRAM chips on ELPT860 board
  175. */
  176. upmconfig(UPMA, (uint *)init_sdram_table,
  177. sizeof(init_sdram_table)/sizeof(uint));
  178. memctl->memc_mptpr = 0x0200;
  179. memctl->memc_mamr = 0x18002111;
  180. memctl->memc_mar = 0x00000088;
  181. memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
  182. upmconfig(UPMA, (uint *)sdram_table,
  183. sizeof(sdram_table)/sizeof(uint));
  184. /*
  185. * Preliminary prescaler for refresh (depends on number of
  186. * banks): This value is selected for four cycles every 62.4 us
  187. * with two SDRAM banks or four cycles every 31.2 us with one
  188. * bank. It will be adjusted after memory sizing.
  189. */
  190. memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
  191. /*
  192. * The following value is used as an address (i.e. opcode) for
  193. * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
  194. * the port size is 32bit the SDRAM does NOT "see" the lower two
  195. * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
  196. * MICRON SDRAMs:
  197. * -> 0 00 010 0 010
  198. * | | | | +- Burst Length = 4
  199. * | | | +----- Burst Type = Sequential
  200. * | | +------- CAS Latency = 2
  201. * | +----------- Operating Mode = Standard
  202. * +-------------- Write Burst Mode = Programmed Burst Length
  203. */
  204. memctl->memc_mar = 0x00000088;
  205. /*
  206. * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
  207. * preliminary addresses - these have to be modified after the
  208. * SDRAM size has been determined.
  209. */
  210. memctl->memc_or1 = CFG_OR1_PRELIM;
  211. memctl->memc_br1 = CFG_BR1_PRELIM;
  212. memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
  213. udelay (200);
  214. /* perform SDRAM initializsation sequence */
  215. memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
  216. udelay (1);
  217. memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
  218. udelay (1);
  219. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  220. udelay (1000);
  221. /*
  222. * Check Bank 0 Memory Size for re-configuration
  223. *
  224. * try 8 column mode
  225. */
  226. size8 = dram_size (CFG_MAMR_8COL,
  227. (ulong *) SDRAM_BASE1_PRELIM,
  228. SDRAM_MAX_SIZE);
  229. udelay (1000);
  230. /*
  231. * try 9 column mode
  232. */
  233. size9 = dram_size (CFG_MAMR_9COL,
  234. (ulong *) SDRAM_BASE1_PRELIM,
  235. SDRAM_MAX_SIZE);
  236. if ( size8 < size9 ) /* leave configuration at 9 columns */
  237. {
  238. size_b0 = size9;
  239. /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
  240. }
  241. else /* back to 8 columns */
  242. {
  243. size_b0 = size8;
  244. memctl->memc_mamr = CFG_MAMR_8COL;
  245. udelay (500);
  246. /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
  247. }
  248. udelay (1000);
  249. /*
  250. * Adjust refresh rate depending on SDRAM type, both banks
  251. * For types > 128 MBit leave it at the current (fast) rate
  252. */
  253. if ( size_b0 < 0x02000000 )
  254. {
  255. /* reduce to 15.6 us (62.4 us / quad) */
  256. memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
  257. udelay (1000);
  258. }
  259. /*
  260. * Final mapping: map bigger bank first
  261. */
  262. memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
  263. memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
  264. {
  265. unsigned long reg;
  266. /* adjust refresh rate depending on SDRAM type, one bank */
  267. reg = memctl->memc_mptpr;
  268. reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
  269. memctl->memc_mptpr = reg;
  270. }
  271. udelay(10000);
  272. return (size_b0);
  273. }
  274. /* ------------------------------------------------------------------------- */
  275. /*
  276. * Check memory range for valid RAM. A simple memory test determines
  277. * the actually available RAM size between addresses `base' and
  278. * `base + maxsize'. Some (not all) hardware errors are detected:
  279. * - short between address lines
  280. * - short between data lines
  281. */
  282. static long int
  283. dram_size (long int mamr_value,
  284. long int *base,
  285. long int maxsize)
  286. {
  287. volatile immap_t *immap = (immap_t *)CFG_IMMR;
  288. volatile memctl8xx_t *memctl = &immap->im_memctl;
  289. volatile long int *addr;
  290. ulong cnt, val;
  291. ulong save[32]; /* to make test non-destructive */
  292. unsigned char i = 0;
  293. memctl->memc_mamr = mamr_value;
  294. for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
  295. {
  296. addr = base + cnt; /* pointer arith! */
  297. save[i++] = *addr;
  298. *addr = ~cnt;
  299. }
  300. /* write 0 to base address */
  301. addr = base;
  302. save[i] = *addr;
  303. *addr = 0;
  304. /* check at base address */
  305. if ( (val = *addr) != 0 )
  306. {
  307. *addr = save[i];
  308. return (0);
  309. }
  310. for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
  311. {
  312. addr = base + cnt; /* pointer arith! */
  313. val = *addr;
  314. *addr = save[--i];
  315. if ( val != (~cnt) )
  316. {
  317. return (cnt * sizeof(long));
  318. }
  319. }
  320. return (maxsize);
  321. }
  322. /* ------------------------------------------------------------------------- */
  323. #define CFG_PA1 0x4000
  324. #define CFG_PA2 0x2000
  325. #define CFG_LBKs (CFG_PA2 | CFG_PA1)
  326. void
  327. reset_phy (void)
  328. {
  329. volatile immap_t *immr = (immap_t *) CFG_IMMR;
  330. /*
  331. * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
  332. * and no AUI loopback
  333. */
  334. immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
  335. immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
  336. immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
  337. }