spl_minimal.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm-offsets.h>
  7. #include <clock_legacy.h>
  8. #include <mpc83xx.h>
  9. #include <time.h>
  10. #include "lblaw/lblaw.h"
  11. #include "elbc/elbc.h"
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /*
  14. * Breathe some life into the CPU...
  15. *
  16. * Set up the memory map,
  17. * initialize a bunch of registers,
  18. * initialize the UPM's
  19. */
  20. void cpu_init_f (volatile immap_t * im)
  21. {
  22. /* Pointer is writable since we allocated a register for it */
  23. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  24. /* global data region was cleared in start.S */
  25. /* system performance tweaking */
  26. #ifndef CONFIG_ACR_PIPE_DEP_UNSET
  27. /* Arbiter pipeline depth */
  28. im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  29. CONFIG_ACR_PIPE_DEP;
  30. #endif
  31. #ifndef CONFIG_ACR_RPTCNT_UNSET
  32. /* Arbiter repeat count */
  33. im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  34. CONFIG_ACR_RPTCNT;
  35. #endif
  36. #ifdef CONFIG_SYS_SPCR_OPT
  37. /* Optimize transactions between CSB and other devices */
  38. im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  39. (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
  40. #endif
  41. /* Enable Time Base & Decrementer (so we will have udelay()) */
  42. im->sysconf.spcr |= SPCR_TBEN;
  43. /* DDR control driver register */
  44. #ifdef CONFIG_SYS_DDRCDR
  45. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
  46. #endif
  47. /* Output buffer impedance register */
  48. #ifdef CONFIG_SYS_OBIR
  49. im->sysconf.obir = CONFIG_SYS_OBIR;
  50. #endif
  51. /*
  52. * Memory Controller:
  53. */
  54. /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
  55. * addresses - these have to be modified later when FLASH size
  56. * has been determined
  57. */
  58. #if defined(CONFIG_SYS_NAND_BR_PRELIM) \
  59. && defined(CONFIG_SYS_NAND_OR_PRELIM) \
  60. && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
  61. && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
  62. set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  63. set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  64. im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
  65. im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
  66. #else
  67. #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
  68. #endif
  69. }
  70. /*
  71. * Get timebase clock frequency (like cpu_clk in Hz)
  72. */
  73. unsigned long get_tbclk(void)
  74. {
  75. return (gd->bus_clk + 3L) / 4L;
  76. }
  77. void puts(const char *str)
  78. {
  79. while (*str)
  80. putc(*str++);
  81. }
  82. ulong get_bus_freq(ulong dummy)
  83. {
  84. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  85. u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  86. return CONFIG_SYS_CLK_FREQ * spmf;
  87. }