bubinga.h 16 KB

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  1. /*
  2. * (C) Copyright 2000-2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
  35. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  36. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  37. #define CONFIG_NO_SERIAL_EEPROM
  38. /*#undef CONFIG_NO_SERIAL_EEPROM*/
  39. /*----------------------------------------------------------------------------*/
  40. #ifdef CONFIG_NO_SERIAL_EEPROM
  41. /*
  42. !-------------------------------------------------------------------------------
  43. ! Defines for entry options.
  44. ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  45. ! are plugged in the board will be utilized as non-ECC DIMMs.
  46. !-------------------------------------------------------------------------------
  47. */
  48. #define AUTO_MEMORY_CONFIG
  49. #define DIMM_READ_ADDR 0xAB
  50. #define DIMM_WRITE_ADDR 0xAA
  51. /*
  52. !-------------------------------------------------------------------------------
  53. ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  54. ! assuming a 33MHz input clock to the 405EP from the C9531.
  55. !-------------------------------------------------------------------------------
  56. */
  57. #define PLLMR0_DEFAULT PLLMR0_266_133_66
  58. #define PLLMR1_DEFAULT PLLMR1_266_133_66
  59. #endif
  60. /*----------------------------------------------------------------------------*/
  61. /*
  62. * Define here the location of the environment variables (FLASH or NVRAM).
  63. * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  64. * supported for backward compatibility.
  65. */
  66. #if 1
  67. #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  68. #else
  69. #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  70. #endif
  71. #define CONFIG_PREBOOT "echo;" \
  72. "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  73. "echo"
  74. #undef CONFIG_BOOTARGS
  75. #define CONFIG_EXTRA_ENV_SETTINGS \
  76. "netdev=eth0\0" \
  77. "hostname=bubinga\0" \
  78. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  79. "nfsroot=$(serverip):$(rootpath)\0" \
  80. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  81. "addip=setenv bootargs $(bootargs) " \
  82. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  83. ":$(hostname):$(netdev):off panic=1\0" \
  84. "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
  85. "flash_nfs=run nfsargs addip addtty;" \
  86. "bootm $(kernel_addr)\0" \
  87. "flash_self=run ramargs addip addtty;" \
  88. "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  89. "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
  90. "bootm\0" \
  91. "rootpath=/opt/eldk/ppc_4xx\0" \
  92. "bootfile=/tftpboot/bubinga/uImage\0" \
  93. "kernel_addr=fff80000\0" \
  94. "ramdisk_addr=fff90000\0" \
  95. "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
  96. "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
  97. "cp.b 100000 fffc0000 40000;" \
  98. "setenv filesize;saveenv\0" \
  99. "upd=run load;run update\0" \
  100. ""
  101. #define CONFIG_BOOTCOMMAND "run net_nfs"
  102. #if 0
  103. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  104. #else
  105. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  106. #endif
  107. #define CONFIG_BAUDRATE 115200
  108. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  109. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  110. #define CONFIG_MII 1 /* MII PHY management */
  111. #define CONFIG_PHY_ADDR 1 /* PHY address */
  112. #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
  113. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  114. CFG_CMD_ASKENV | \
  115. CFG_CMD_CACHE | \
  116. CFG_CMD_DATE | \
  117. CFG_CMD_DHCP | \
  118. CFG_CMD_EEPROM | \
  119. CFG_CMD_ELF | \
  120. CFG_CMD_I2C | \
  121. CFG_CMD_IRQ | \
  122. CFG_CMD_MII | \
  123. CFG_CMD_NET | \
  124. CFG_CMD_PCI | \
  125. CFG_CMD_PING | \
  126. CFG_CMD_REGINFO | \
  127. CFG_CMD_SDRAM | \
  128. CFG_CMD_SNTP )
  129. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  130. #include <cmd_confdefs.h>
  131. #undef CONFIG_WATCHDOG /* watchdog disabled */
  132. #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
  133. /*
  134. * Miscellaneous configurable options
  135. */
  136. #define CFG_LONGHELP /* undef to save memory */
  137. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  138. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  139. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  140. #else
  141. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  142. #endif
  143. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  144. #define CFG_MAXARGS 16 /* max number of command args */
  145. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  146. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  147. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  148. /*
  149. * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  150. * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
  151. * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
  152. * The Linux BASE_BAUD define should match this configuration.
  153. * baseBaud = cpuClock/(uartDivisor*16)
  154. * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
  155. * set Linux BASE_BAUD to 403200.
  156. */
  157. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  158. #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
  159. #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
  160. #define CFG_BASE_BAUD 691200
  161. /* The following table includes the supported baudrates */
  162. #define CFG_BAUDRATE_TABLE \
  163. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  164. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  165. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  166. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  167. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  168. #define CONFIG_LOOPW 1 /* enable loopw command */
  169. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  170. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  171. #define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
  172. /*-----------------------------------------------------------------------
  173. * I2C stuff
  174. *-----------------------------------------------------------------------
  175. */
  176. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  177. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  178. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  179. #define CFG_I2C_SLAVE 0x7F
  180. #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
  181. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
  182. #if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
  183. #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
  184. #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  185. #endif
  186. /*-----------------------------------------------------------------------
  187. * PCI stuff
  188. *-----------------------------------------------------------------------
  189. */
  190. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  191. #define PCI_HOST_FORCE 1 /* configure as pci host */
  192. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  193. #define CONFIG_PCI /* include pci support */
  194. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  195. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  196. /* resource configuration */
  197. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  198. #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
  199. #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
  200. #define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
  201. #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  202. #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  203. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  204. #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
  205. #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
  206. #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  207. /*-----------------------------------------------------------------------
  208. * External peripheral base address
  209. *-----------------------------------------------------------------------
  210. */
  211. #define CFG_KEY_REG_BASE_ADDR 0xF0100000
  212. #define CFG_IR_REG_BASE_ADDR 0xF0200000
  213. #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
  214. /*-----------------------------------------------------------------------
  215. * Start addresses for the final memory configuration
  216. * (Set up by the startup code)
  217. * Please note that CFG_SDRAM_BASE _must_ start at 0
  218. */
  219. #define CFG_SDRAM_BASE 0x00000000
  220. #define CFG_SRAM_BASE 0xFFF00000
  221. #define CFG_FLASH_BASE 0xFFF80000
  222. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  223. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  224. #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
  225. /*
  226. * For booting Linux, the board info and command line data
  227. * have to be in the first 8 MB of memory, since this is
  228. * the maximum mapped by the Linux kernel during initialization.
  229. */
  230. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  231. /*-----------------------------------------------------------------------
  232. * FLASH organization
  233. */
  234. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  235. #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  236. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  237. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  238. #define CFG_FLASH_ADDR0 0x5555
  239. #define CFG_FLASH_ADDR1 0x2aaa
  240. #define CFG_FLASH_WORD_SIZE unsigned char
  241. #ifdef CFG_ENV_IS_IN_FLASH
  242. #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
  243. #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
  244. #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  245. /* Address and size of Redundant Environment Sector */
  246. #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
  247. #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  248. #endif /* CFG_ENV_IS_IN_FLASH */
  249. /*-----------------------------------------------------------------------
  250. * NVRAM organization
  251. */
  252. #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
  253. #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
  254. #ifdef CFG_ENV_IS_IN_NVRAM
  255. #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
  256. #define CFG_ENV_ADDR \
  257. (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
  258. #endif
  259. /*-----------------------------------------------------------------------
  260. * Cache Configuration
  261. */
  262. #define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
  263. #define CFG_CACHELINE_SIZE 32 /* ... */
  264. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  265. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  266. #endif
  267. /*
  268. * Init Memory Controller:
  269. *
  270. * BR0/1 and OR0/1 (FLASH)
  271. */
  272. #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
  273. #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
  274. /*-----------------------------------------------------------------------
  275. * Definitions for initial stack pointer and data area (in data cache)
  276. */
  277. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  278. #define CFG_TEMP_STACK_OCM 1
  279. /* On Chip Memory location */
  280. #define CFG_OCM_DATA_ADDR 0xF8000000
  281. #define CFG_OCM_DATA_SIZE 0x1000
  282. #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
  283. #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  284. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  285. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  286. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  287. /*-----------------------------------------------------------------------
  288. * External Bus Controller (EBC) Setup
  289. */
  290. /* Memory Bank 0 (Flash/SRAM) initialization */
  291. #define CFG_EBC_PB0AP 0x04006000
  292. #define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
  293. /* Memory Bank 1 (NVRAM/RTC) initialization */
  294. #define CFG_EBC_PB1AP 0x04041000
  295. #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  296. /* Memory Bank 2 (not used) initialization */
  297. #define CFG_EBC_PB2AP 0x00000000
  298. #define CFG_EBC_PB2CR 0x00000000
  299. /* Memory Bank 2 (not used) initialization */
  300. #define CFG_EBC_PB3AP 0x00000000
  301. #define CFG_EBC_PB3CR 0x00000000
  302. /* Memory Bank 4 (FPGA regs) initialization */
  303. #define CFG_EBC_PB4AP 0x01815000
  304. #define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
  305. /*-----------------------------------------------------------------------
  306. * Definitions for Serial Presence Detect EEPROM address
  307. * (to get SDRAM settings)
  308. */
  309. #define SPD_EEPROM_ADDRESS 0x55
  310. /*-----------------------------------------------------------------------
  311. * Definitions for GPIO setup (PPC405EP specific)
  312. *
  313. * GPIO0[0] - External Bus Controller BLAST output
  314. * GPIO0[1-9] - Instruction trace outputs
  315. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  316. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
  317. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  318. * GPIO0[24-27] - UART0 control signal inputs/outputs
  319. * GPIO0[28-29] - UART1 data signal input/output
  320. * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  321. */
  322. #define CFG_GPIO0_OSRH 0x55555555
  323. #define CFG_GPIO0_OSRL 0x40000110
  324. #define CFG_GPIO0_ISR1H 0x00000000
  325. #define CFG_GPIO0_ISR1L 0x15555445
  326. #define CFG_GPIO0_TSRH 0x00000000
  327. #define CFG_GPIO0_TSRL 0x00000000
  328. #define CFG_GPIO0_TCR 0xFFFF8014
  329. /*-----------------------------------------------------------------------
  330. * Some BUBINGA stuff...
  331. */
  332. #define NVRAM_BASE 0xF0000000
  333. #define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
  334. #define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
  335. #define NVRVFY1 0x4f532d4f /* used to determine if state data in */
  336. #define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
  337. #define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
  338. #define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
  339. #define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
  340. #define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
  341. #define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
  342. #define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
  343. #define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
  344. #define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
  345. #define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
  346. #define FPGA_REG1_CLOCK_BIT_SHIFT 4
  347. #define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
  348. #define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
  349. #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
  350. #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
  351. /*
  352. * Internal Definitions
  353. *
  354. * Boot Flags
  355. */
  356. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  357. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  358. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  359. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  360. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  361. #endif
  362. #endif /* __CONFIG_H */