bamboo.h 11 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /************************************************************************
  24. * bamboo.h - configuration for BAMBOO board
  25. ***********************************************************************/
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*-----------------------------------------------------------------------
  29. * High Level Configuration Options
  30. *----------------------------------------------------------------------*/
  31. #define CONFIG_BAMBOO 1 /* Board is BAMBOO */
  32. #define CONFIG_440_EP 1 /* Specific PPC440EP support */
  33. #define CONFIG_4xx 1 /* ... PPC4xx family */
  34. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  35. #undef CFG_DRAM_TEST /* disable - takes long time! */
  36. //#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
  37. #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
  38. /*-----------------------------------------------------------------------
  39. * Base addresses -- Note these are effective addresses where the
  40. * actual resources get mapped (not physical addresses)
  41. *----------------------------------------------------------------------*/
  42. #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
  43. #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
  44. #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  45. #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
  46. #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
  47. #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
  48. #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
  49. /*Don't change either of these*/
  50. #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
  51. #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
  52. /*Don't change either of these*/
  53. #define CFG_USB_DEVICE 0x50000000
  54. #define CFG_NVRAM_BASE_ADDR 0x80000000
  55. #define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
  56. /*-----------------------------------------------------------------------
  57. * Initial RAM & stack pointer (placed in SDRAM)
  58. *----------------------------------------------------------------------*/
  59. #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
  60. #define CFG_INIT_RAM_END 0x2000
  61. #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
  62. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  63. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  64. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  65. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
  66. #define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
  67. //#define CFG_SDRAM_BANKS (2)
  68. #define CFG_SDRAM_BANKS (1)
  69. /*-----------------------------------------------------------------------
  70. * Serial Port
  71. *----------------------------------------------------------------------*/
  72. #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
  73. #define CONFIG_BAUDRATE 115200
  74. #define CONFIG_SERIAL_MULTI 1
  75. /*define this if you want console on UART1*/
  76. #undef CONFIG_UART1_CONSOLE
  77. #define CFG_BAUDRATE_TABLE \
  78. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  79. /*-----------------------------------------------------------------------
  80. * NVRAM/RTC
  81. *
  82. * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
  83. * The DS1558 code assumes this condition
  84. *
  85. *----------------------------------------------------------------------*/
  86. #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
  87. #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
  88. /*-----------------------------------------------------------------------
  89. * FLASH related
  90. *----------------------------------------------------------------------*/
  91. #if 0 /* test-only */
  92. #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
  93. #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
  94. #undef CFG_FLASH_CHECKSUM
  95. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  96. #define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
  97. #else
  98. #define CFG_FLASH_CFI /* The flash is CFI compatible */
  99. #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
  100. #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
  101. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  102. #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  103. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  104. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  105. #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  106. #endif
  107. /*-----------------------------------------------------------------------
  108. * DDR SDRAM
  109. *----------------------------------------------------------------------*/
  110. #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
  111. /*-----------------------------------------------------------------------
  112. * I2C
  113. *----------------------------------------------------------------------*/
  114. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  115. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  116. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  117. #define CFG_I2C_SLAVE 0x7F
  118. /*-----------------------------------------------------------------------
  119. * Environment
  120. *----------------------------------------------------------------------*/
  121. #undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
  122. #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
  123. #define CFG_ENV_IS_IN_EEPROM 1
  124. /* Define to allow the user to overwrite serial and ethaddr */
  125. #define CONFIG_ENV_OVERWRITE
  126. #define CFG_I2C_MULTI_EEPROMS
  127. #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
  128. #define CFG_ENV_OFFSET 0x0
  129. #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
  130. #define CFG_I2C_EEPROM_ADDR_LEN 1
  131. #define CFG_EEPROM_PAGE_WRITE_ENABLE
  132. #define CFG_EEPROM_PAGE_WRITE_BITS 3
  133. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
  134. #define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
  135. #define CONFIG_BOOTDELAY 3 /* disable autoboot */
  136. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  137. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  138. #define CONFIG_MII 1 /* MII PHY management */
  139. #define CONFIG_NET_MULTI 1 /* required for netconsole */
  140. #define CONFIG_PHY1_ADDR 3
  141. #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
  142. #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
  143. #define CONFIG_NETMASK 255.255.255.0
  144. #define CONFIG_IPADDR 10.0.4.251
  145. #define CONFIG_ETHADDR 00:10:EC:00:12:34
  146. #define CONFIG_ETH1ADDR 00:10:EC:00:12:35
  147. #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
  148. #define CONFIG_SERVERIP 10.0.4.115
  149. /* Partitions */
  150. #define CONFIG_MAC_PARTITION
  151. #define CONFIG_DOS_PARTITION
  152. #define CONFIG_ISO_PARTITION
  153. #ifdef CONFIG_440_EP
  154. /* USB */
  155. #define CONFIG_USB_OHCI
  156. #define CONFIG_USB_STORAGE
  157. /*Comment this out to enable USB 1.1 device*/
  158. #define USB_2_0_DEVICE
  159. #endif /*CONFIG_440_EP*/
  160. #ifdef DEBUG
  161. #define CONFIG_PANIC_HANG
  162. #else
  163. #define CONFIG_HW_WATCHDOG /* watchdog */
  164. #endif
  165. #ifdef CONFIG_440_EP
  166. /* Need to define POST */
  167. #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
  168. CFG_CMD_DATE | \
  169. CFG_CMD_DHCP | \
  170. CFG_CMD_DIAG | \
  171. CFG_CMD_ECHO | \
  172. CFG_CMD_EEPROM | \
  173. CFG_CMD_ELF | \
  174. /* CFG_CMD_EXT2 |*/ \
  175. /* CFG_CMD_FAT |*/ \
  176. CFG_CMD_I2C | \
  177. /* CFG_CMD_IDE |*/ \
  178. CFG_CMD_IRQ | \
  179. /* CFG_CMD_KGDB |*/ \
  180. CFG_CMD_MII | \
  181. CFG_CMD_PCI | \
  182. CFG_CMD_PING | \
  183. CFG_CMD_REGINFO | \
  184. CFG_CMD_SDRAM | \
  185. CFG_CMD_FLASH | \
  186. /* CFG_CMD_SPI |*/ \
  187. CFG_CMD_USB | \
  188. 0 ) & ~CFG_CMD_IMLS)
  189. #else
  190. #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
  191. CFG_CMD_DATE | \
  192. CFG_CMD_DHCP | \
  193. CFG_CMD_DIAG | \
  194. CFG_CMD_ECHO | \
  195. CFG_CMD_EEPROM | \
  196. CFG_CMD_ELF | \
  197. /* CFG_CMD_EXT2 |*/ \
  198. /* CFG_CMD_FAT |*/ \
  199. CFG_CMD_I2C | \
  200. /* CFG_CMD_IDE |*/ \
  201. CFG_CMD_IRQ | \
  202. /* CFG_CMD_KGDB |*/ \
  203. CFG_CMD_MII | \
  204. CFG_CMD_PCI | \
  205. CFG_CMD_PING | \
  206. CFG_CMD_REGINFO | \
  207. CFG_CMD_SDRAM | \
  208. CFG_CMD_FLASH | \
  209. /* CFG_CMD_SPI |*/ \
  210. 0 ) & ~CFG_CMD_IMLS)
  211. #endif
  212. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  213. #include <cmd_confdefs.h>
  214. /*
  215. * Miscellaneous configurable options
  216. */
  217. #define CFG_LONGHELP /* undef to save memory */
  218. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  219. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  220. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  221. #else
  222. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  223. #endif
  224. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  225. #define CFG_MAXARGS 16 /* max number of command args */
  226. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  227. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  228. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  229. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  230. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  231. #define CONFIG_LYNXKDI 1 /* support kdi files */
  232. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  233. /*-----------------------------------------------------------------------
  234. * PCI stuff
  235. *-----------------------------------------------------------------------
  236. */
  237. /* General PCI */
  238. #define CONFIG_PCI /* include pci support */
  239. #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
  240. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  241. #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
  242. /* Board-specific PCI */
  243. #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
  244. #define CFG_PCI_TARGET_INIT
  245. #define CFG_PCI_MASTER_INIT
  246. #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
  247. #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
  248. /*
  249. * For booting Linux, the board info and command line data
  250. * have to be in the first 8 MB of memory, since this is
  251. * the maximum mapped by the Linux kernel during initialization.
  252. */
  253. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  254. /*-----------------------------------------------------------------------
  255. * Cache Configuration
  256. */
  257. #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  258. #define CFG_CACHELINE_SIZE 32 /* ... */
  259. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  260. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  261. #endif
  262. /*
  263. * Internal Definitions
  264. *
  265. * Boot Flags
  266. */
  267. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  268. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  269. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  270. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  271. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  272. #endif
  273. #endif /* __CONFIG_H */