ebony.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297
  1. /*
  2. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/processor.h>
  24. #include <spd_sdram.h>
  25. #define BOOT_SMALL_FLASH 32 /* 00100000 */
  26. #define FLASH_ONBD_N 2 /* 00000010 */
  27. #define FLASH_SRAM_SEL 1 /* 00000001 */
  28. long int fixed_sdram(void);
  29. int board_early_init_f(void)
  30. {
  31. uint reg;
  32. unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
  33. unsigned char status;
  34. /*--------------------------------------------------------------------
  35. * Setup the external bus controller/chip selects
  36. *-------------------------------------------------------------------*/
  37. mtdcr(ebccfga, xbcfg);
  38. reg = mfdcr(ebccfgd);
  39. mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
  40. mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
  41. mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
  42. mtebc(pb7ap, 0x01015280); /* FPGA registers */
  43. mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
  44. /* read FPGA_REG0 and set the bus controller */
  45. status = *fpga_base;
  46. if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
  47. mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
  48. mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
  49. mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
  50. mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
  51. } else {
  52. mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
  53. mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
  54. /* set CS2 if FLASH_ONBD_N == 0 */
  55. if (!(status & FLASH_ONBD_N)) {
  56. mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
  57. mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
  58. }
  59. }
  60. /*--------------------------------------------------------------------
  61. * Setup the interrupt controller polarities, triggers, etc.
  62. *-------------------------------------------------------------------*/
  63. mtdcr(uic0sr, 0xffffffff); /* clear all */
  64. mtdcr(uic0er, 0x00000000); /* disable all */
  65. mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
  66. mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
  67. mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
  68. mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  69. mtdcr(uic0sr, 0xffffffff); /* clear all */
  70. mtdcr(uic1sr, 0xffffffff); /* clear all */
  71. mtdcr(uic1er, 0x00000000); /* disable all */
  72. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  73. mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
  74. mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
  75. mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  76. mtdcr(uic1sr, 0xffffffff); /* clear all */
  77. return 0;
  78. }
  79. int checkboard(void)
  80. {
  81. sys_info_t sysinfo;
  82. unsigned char *s = getenv("serial#");
  83. get_sys_info(&sysinfo);
  84. printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
  85. if (s != NULL) {
  86. puts(", serial# ");
  87. puts(s);
  88. }
  89. putc('\n');
  90. printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
  91. printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
  92. printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
  93. printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
  94. printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
  95. return (0);
  96. }
  97. long int initdram(int board_type)
  98. {
  99. long dram_size = 0;
  100. #if defined(CONFIG_SPD_EEPROM)
  101. dram_size = spd_sdram(0);
  102. #else
  103. dram_size = fixed_sdram();
  104. #endif
  105. return dram_size;
  106. }
  107. #if defined(CFG_DRAM_TEST)
  108. int testdram(void)
  109. {
  110. uint *pstart = (uint *) 0x00000000;
  111. uint *pend = (uint *) 0x08000000;
  112. uint *p;
  113. for (p = pstart; p < pend; p++)
  114. *p = 0xaaaaaaaa;
  115. for (p = pstart; p < pend; p++) {
  116. if (*p != 0xaaaaaaaa) {
  117. printf("SDRAM test fails at: %08x\n", (uint) p);
  118. return 1;
  119. }
  120. }
  121. for (p = pstart; p < pend; p++)
  122. *p = 0x55555555;
  123. for (p = pstart; p < pend; p++) {
  124. if (*p != 0x55555555) {
  125. printf("SDRAM test fails at: %08x\n", (uint) p);
  126. return 1;
  127. }
  128. }
  129. return 0;
  130. }
  131. #endif
  132. #if !defined(CONFIG_SPD_EEPROM)
  133. /*************************************************************************
  134. * fixed sdram init -- doesn't use serial presence detect.
  135. *
  136. * Assumes: 128 MB, non-ECC, non-registered
  137. * PLB @ 133 MHz
  138. *
  139. ************************************************************************/
  140. long int fixed_sdram(void)
  141. {
  142. uint reg;
  143. /*--------------------------------------------------------------------
  144. * Setup some default
  145. *------------------------------------------------------------------*/
  146. mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
  147. mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
  148. mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
  149. mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
  150. mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
  151. /*--------------------------------------------------------------------
  152. * Setup for board-specific specific mem
  153. *------------------------------------------------------------------*/
  154. /*
  155. * Following for CAS Latency = 2.5 @ 133 MHz PLB
  156. */
  157. mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
  158. mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
  159. /* RA=10 RD=3 */
  160. mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
  161. mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
  162. mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
  163. udelay(400); /* Delay 200 usecs (min) */
  164. /*--------------------------------------------------------------------
  165. * Enable the controller, then wait for DCEN to complete
  166. *------------------------------------------------------------------*/
  167. mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
  168. for (;;) {
  169. mfsdram(mem_mcsts, reg);
  170. if (reg & 0x80000000)
  171. break;
  172. }
  173. return (128 * 1024 * 1024); /* 128 MB */
  174. }
  175. #endif /* !defined(CONFIG_SPD_EEPROM) */
  176. /*************************************************************************
  177. * pci_pre_init
  178. *
  179. * This routine is called just prior to registering the hose and gives
  180. * the board the opportunity to check things. Returning a value of zero
  181. * indicates that things are bad & PCI initialization should be aborted.
  182. *
  183. * Different boards may wish to customize the pci controller structure
  184. * (add regions, override default access routines, etc) or perform
  185. * certain pre-initialization actions.
  186. *
  187. ************************************************************************/
  188. #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
  189. int pci_pre_init(struct pci_controller *hose)
  190. {
  191. unsigned long strap;
  192. /*--------------------------------------------------------------------------+
  193. * The ebony board is always configured as the host & requires the
  194. * PCI arbiter to be enabled.
  195. *--------------------------------------------------------------------------*/
  196. strap = mfdcr(cpc0_strp1);
  197. if ((strap & 0x00100000) == 0) {
  198. printf("PCI: CPC0_STRP1[PAE] not set.\n");
  199. return 0;
  200. }
  201. return 1;
  202. }
  203. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
  204. /*************************************************************************
  205. * pci_target_init
  206. *
  207. * The bootstrap configuration provides default settings for the pci
  208. * inbound map (PIM). But the bootstrap config choices are limited and
  209. * may not be sufficient for a given board.
  210. *
  211. ************************************************************************/
  212. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  213. void pci_target_init(struct pci_controller *hose)
  214. {
  215. DECLARE_GLOBAL_DATA_PTR;
  216. /*--------------------------------------------------------------------------+
  217. * Disable everything
  218. *--------------------------------------------------------------------------*/
  219. out32r(PCIX0_PIM0SA, 0); /* disable */
  220. out32r(PCIX0_PIM1SA, 0); /* disable */
  221. out32r(PCIX0_PIM2SA, 0); /* disable */
  222. out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
  223. /*--------------------------------------------------------------------------+
  224. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
  225. * options to not support sizes such as 128/256 MB.
  226. *--------------------------------------------------------------------------*/
  227. out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
  228. out32r(PCIX0_PIM0LAH, 0);
  229. out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
  230. out32r(PCIX0_BAR0, 0);
  231. /*--------------------------------------------------------------------------+
  232. * Program the board's subsystem id/vendor id
  233. *--------------------------------------------------------------------------*/
  234. out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
  235. out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
  236. out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
  237. }
  238. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  239. /*************************************************************************
  240. * is_pci_host
  241. *
  242. * This routine is called to determine if a pci scan should be
  243. * performed. With various hardware environments (especially cPCI and
  244. * PPMC) it's insufficient to depend on the state of the arbiter enable
  245. * bit in the strap register, or generic host/adapter assumptions.
  246. *
  247. * Rather than hard-code a bad assumption in the general 440 code, the
  248. * 440 pci code requires the board to decide at runtime.
  249. *
  250. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  251. *
  252. *
  253. ************************************************************************/
  254. #if defined(CONFIG_PCI)
  255. int is_pci_host(struct pci_controller *hose)
  256. {
  257. /* The ebony board is always configured as host. */
  258. return (1);
  259. }
  260. #endif /* defined(CONFIG_PCI) */