bamboo.c 15 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/processor.h>
  25. #include <spd_sdram.h>
  26. int board_early_init_f(void)
  27. {
  28. register uint reg;
  29. /*--------------------------------------------------------------------
  30. * Setup the external bus controller/chip selects
  31. *-------------------------------------------------------------------*/
  32. mtdcr(ebccfga, xbcfg);
  33. reg = mfdcr(ebccfgd);
  34. mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
  35. #if 0 /* test-only */
  36. mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
  37. mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
  38. mtebc(pb1ap, 0x00000000);
  39. mtebc(pb1cr, 0x00000000);
  40. mtebc(pb2ap, 0x04814500);
  41. /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
  42. #else
  43. mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
  44. mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
  45. #endif
  46. mtebc(pb3ap, 0x00000000);
  47. mtebc(pb3cr, 0x00000000);
  48. mtebc(pb4ap, 0x00000000);
  49. mtebc(pb4cr, 0x00000000);
  50. mtebc(pb5ap, 0x00000000);
  51. mtebc(pb5cr, 0x00000000);
  52. /*--------------------------------------------------------------------
  53. * Setup the interrupt controller polarities, triggers, etc.
  54. *-------------------------------------------------------------------*/
  55. mtdcr(uic0sr, 0xffffffff); /* clear all */
  56. mtdcr(uic0er, 0x00000000); /* disable all */
  57. mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
  58. mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
  59. mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
  60. mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  61. mtdcr(uic0sr, 0xffffffff); /* clear all */
  62. mtdcr(uic1sr, 0xffffffff); /* clear all */
  63. mtdcr(uic1er, 0x00000000); /* disable all */
  64. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  65. mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
  66. mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
  67. mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  68. mtdcr(uic1sr, 0xffffffff); /* clear all */
  69. /*--------------------------------------------------------------------
  70. * Setup the GPIO pins
  71. *-------------------------------------------------------------------*/
  72. /*CPLD cs */
  73. /*setup Address lines for flash sizes larger than 16Meg. */
  74. out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
  75. out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
  76. out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  77. /*setup emac */
  78. out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  79. out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  80. out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  81. out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  82. out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  83. /*UART1 */
  84. out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  85. out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  86. out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  87. /*setup USB 2.0 */
  88. out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  89. out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  90. out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  91. out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  92. out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  93. /*--------------------------------------------------------------------
  94. * Setup other serial configuration
  95. *-------------------------------------------------------------------*/
  96. mfsdr(sdr_pci0, reg);
  97. mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
  98. mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
  99. mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
  100. #if 0 /* test-only */
  101. /*clear tmrclk divisor */
  102. *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
  103. /*enable ethernet */
  104. *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
  105. /*enable usb 1.1 fs device and remove usb 2.0 reset */
  106. *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
  107. /*get rid of flash write protect */
  108. *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
  109. #endif
  110. return 0;
  111. }
  112. int checkboard(void)
  113. {
  114. sys_info_t sysinfo;
  115. unsigned char *s = getenv("serial#");
  116. get_sys_info(&sysinfo);
  117. printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
  118. if (s != NULL) {
  119. puts(", serial# ");
  120. puts(s);
  121. }
  122. putc('\n');
  123. printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
  124. printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
  125. printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
  126. printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
  127. printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
  128. return (0);
  129. }
  130. /*************************************************************************
  131. * sdram_init -- doesn't use serial presence detect.
  132. *
  133. * Assumes: 256 MB, ECC, non-registered
  134. * PLB @ 133 MHz
  135. *
  136. ************************************************************************/
  137. void sdram_init(void)
  138. {
  139. register uint reg;
  140. /*--------------------------------------------------------------------
  141. * Setup some default
  142. *------------------------------------------------------------------*/
  143. mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
  144. mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
  145. mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
  146. mtsdram(mem_clktr, 0x40000000); /* ?? */
  147. mtsdram(mem_wddctr, 0x40000000); /* ?? */
  148. /*clear this first, if the DDR is enabled by a debugger
  149. then you can not make changes. */
  150. mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
  151. /*--------------------------------------------------------------------
  152. * Setup for board-specific specific mem
  153. *------------------------------------------------------------------*/
  154. /*
  155. * Following for CAS Latency = 2.5 @ 133 MHz PLB
  156. */
  157. mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
  158. mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
  159. mtsdram(mem_tr0, 0x410a4012); /* ?? */
  160. mtsdram(mem_tr1, 0x8080080b); /* ?? */
  161. mtsdram(mem_rtr, 0x04080000); /* ?? */
  162. mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
  163. mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
  164. udelay(400); /* Delay 200 usecs (min) */
  165. /*--------------------------------------------------------------------
  166. * Enable the controller, then wait for DCEN to complete
  167. *------------------------------------------------------------------*/
  168. mtsdram(mem_cfg0, 0x84000000); /* Enable */
  169. for (;;) {
  170. mfsdram(mem_mcsts, reg);
  171. if (reg & 0x80000000)
  172. break;
  173. }
  174. }
  175. /*************************************************************************
  176. * long int initdram
  177. *
  178. ************************************************************************/
  179. long int initdram(int board)
  180. {
  181. sdram_init();
  182. return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
  183. }
  184. #if defined(CFG_DRAM_TEST)
  185. int testdram(void)
  186. {
  187. unsigned long *mem = (unsigned long *)0;
  188. const unsigned long kend = (1024 / sizeof(unsigned long));
  189. unsigned long k, n;
  190. mtmsr(0);
  191. for (k = 0; k < CFG_KBYTES_SDRAM;
  192. ++k, mem += (1024 / sizeof(unsigned long))) {
  193. if ((k & 1023) == 0) {
  194. printf("%3d MB\r", k / 1024);
  195. }
  196. memset(mem, 0xaaaaaaaa, 1024);
  197. for (n = 0; n < kend; ++n) {
  198. if (mem[n] != 0xaaaaaaaa) {
  199. printf("SDRAM test fails at: %08x\n",
  200. (uint) & mem[n]);
  201. return 1;
  202. }
  203. }
  204. memset(mem, 0x55555555, 1024);
  205. for (n = 0; n < kend; ++n) {
  206. if (mem[n] != 0x55555555) {
  207. printf("SDRAM test fails at: %08x\n",
  208. (uint) & mem[n]);
  209. return 1;
  210. }
  211. }
  212. }
  213. printf("SDRAM test passes\n");
  214. return 0;
  215. }
  216. #endif
  217. /*************************************************************************
  218. * pci_pre_init
  219. *
  220. * This routine is called just prior to registering the hose and gives
  221. * the board the opportunity to check things. Returning a value of zero
  222. * indicates that things are bad & PCI initialization should be aborted.
  223. *
  224. * Different boards may wish to customize the pci controller structure
  225. * (add regions, override default access routines, etc) or perform
  226. * certain pre-initialization actions.
  227. *
  228. ************************************************************************/
  229. #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
  230. int pci_pre_init(struct pci_controller *hose)
  231. {
  232. unsigned long strap;
  233. unsigned long addr;
  234. /*--------------------------------------------------------------------------+
  235. * Bamboo is always configured as the host & requires the
  236. * PCI arbiter to be enabled.
  237. *--------------------------------------------------------------------------*/
  238. mfsdr(sdr_sdstp1, strap);
  239. if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
  240. printf("PCI: SDR0_STRP1[PAE] not set.\n");
  241. printf("PCI: Configuration aborted.\n");
  242. return 0;
  243. }
  244. /*-------------------------------------------------------------------------+
  245. | Set priority for all PLB3 devices to 0.
  246. | Set PLB3 arbiter to fair mode.
  247. +-------------------------------------------------------------------------*/
  248. mfsdr(sdr_amp1, addr);
  249. mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
  250. addr = mfdcr(plb3_acr);
  251. mtdcr(plb3_acr, addr | 0x80000000);
  252. /*-------------------------------------------------------------------------+
  253. | Set priority for all PLB4 devices to 0.
  254. +-------------------------------------------------------------------------*/
  255. mfsdr(sdr_amp0, addr);
  256. mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
  257. addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
  258. mtdcr(plb4_acr, addr);
  259. /*-------------------------------------------------------------------------+
  260. | Set Nebula PLB4 arbiter to fair mode.
  261. +-------------------------------------------------------------------------*/
  262. /* Segment0 */
  263. addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
  264. addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
  265. addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
  266. addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
  267. mtdcr(plb0_acr, addr);
  268. /* Segment1 */
  269. addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
  270. addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
  271. addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
  272. addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
  273. mtdcr(plb1_acr, addr);
  274. return 1;
  275. }
  276. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
  277. /*************************************************************************
  278. * pci_target_init
  279. *
  280. * The bootstrap configuration provides default settings for the pci
  281. * inbound map (PIM). But the bootstrap config choices are limited and
  282. * may not be sufficient for a given board.
  283. *
  284. ************************************************************************/
  285. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  286. void pci_target_init(struct pci_controller *hose)
  287. {
  288. /*--------------------------------------------------------------------------+
  289. * Set up Direct MMIO registers
  290. *--------------------------------------------------------------------------*/
  291. /*--------------------------------------------------------------------------+
  292. | PowerPC440 EP PCI Master configuration.
  293. | Map one 1Gig range of PLB/processor addresses to PCI memory space.
  294. | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
  295. | Use byte reversed out routines to handle endianess.
  296. | Make this region non-prefetchable.
  297. +--------------------------------------------------------------------------*/
  298. out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
  299. out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
  300. out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
  301. out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
  302. out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
  303. out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
  304. out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
  305. out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
  306. out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
  307. out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
  308. out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
  309. out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
  310. out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
  311. out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
  312. /*--------------------------------------------------------------------------+
  313. * Set up Configuration registers
  314. *--------------------------------------------------------------------------*/
  315. /* Program the board's subsystem id/vendor id */
  316. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  317. CFG_PCI_SUBSYS_VENDORID);
  318. pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
  319. /* Configure command register as bus master */
  320. pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
  321. /* 240nS PCI clock */
  322. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  323. /* No error reporting */
  324. pci_write_config_word(0, PCI_ERREN, 0);
  325. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  326. }
  327. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  328. /*************************************************************************
  329. * pci_master_init
  330. *
  331. ************************************************************************/
  332. #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
  333. void pci_master_init(struct pci_controller *hose)
  334. {
  335. unsigned short temp_short;
  336. /*--------------------------------------------------------------------------+
  337. | Write the PowerPC440 EP PCI Configuration regs.
  338. | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  339. | Enable PowerPC440 EP to act as a PCI memory target (PTM).
  340. +--------------------------------------------------------------------------*/
  341. pci_read_config_word(0, PCI_COMMAND, &temp_short);
  342. pci_write_config_word(0, PCI_COMMAND,
  343. temp_short | PCI_COMMAND_MASTER |
  344. PCI_COMMAND_MEMORY);
  345. }
  346. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
  347. /*************************************************************************
  348. * is_pci_host
  349. *
  350. * This routine is called to determine if a pci scan should be
  351. * performed. With various hardware environments (especially cPCI and
  352. * PPMC) it's insufficient to depend on the state of the arbiter enable
  353. * bit in the strap register, or generic host/adapter assumptions.
  354. *
  355. * Rather than hard-code a bad assumption in the general 440 code, the
  356. * 440 pci code requires the board to decide at runtime.
  357. *
  358. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  359. *
  360. *
  361. ************************************************************************/
  362. #if defined(CONFIG_PCI)
  363. int is_pci_host(struct pci_controller *hose)
  364. {
  365. /* Bamboo is always configured as host. */
  366. return (1);
  367. }
  368. #endif /* defined(CONFIG_PCI) */
  369. /*************************************************************************
  370. * hw_watchdog_reset
  371. *
  372. * This routine is called to reset (keep alive) the watchdog timer
  373. *
  374. ************************************************************************/
  375. #if defined(CONFIG_HW_WATCHDOG)
  376. void hw_watchdog_reset(void)
  377. {
  378. }
  379. #endif