ast_wdt.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <wdt.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/wdt.h>
  11. #define WDT_AST2500 2500
  12. #define WDT_AST2400 2400
  13. struct ast_wdt_priv {
  14. struct ast_wdt *regs;
  15. };
  16. static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  17. {
  18. struct ast_wdt_priv *priv = dev_get_priv(dev);
  19. ulong driver_data = dev_get_driver_data(dev);
  20. u32 reset_mode = ast_reset_mode_from_flags(flags);
  21. /* 32 bits at 1MHz is 4294967ms */
  22. timeout = min_t(u64, timeout, 4294967);
  23. /* WDT counts in ticks of 1MHz clock. 1ms / 1e3 * 1e6 */
  24. timeout *= 1000;
  25. clrsetbits_le32(&priv->regs->ctrl,
  26. WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
  27. reset_mode << WDT_CTRL_RESET_MODE_SHIFT);
  28. if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
  29. writel(ast_reset_mask_from_flags(flags),
  30. &priv->regs->reset_mask);
  31. writel((u32) timeout, &priv->regs->counter_reload_val);
  32. writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
  33. /*
  34. * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
  35. * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
  36. * read-only
  37. */
  38. setbits_le32(&priv->regs->ctrl,
  39. WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
  40. return 0;
  41. }
  42. static int ast_wdt_stop(struct udevice *dev)
  43. {
  44. struct ast_wdt_priv *priv = dev_get_priv(dev);
  45. clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
  46. writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask);
  47. return 0;
  48. }
  49. static int ast_wdt_reset(struct udevice *dev)
  50. {
  51. struct ast_wdt_priv *priv = dev_get_priv(dev);
  52. writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
  53. return 0;
  54. }
  55. static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
  56. {
  57. struct ast_wdt_priv *priv = dev_get_priv(dev);
  58. int ret;
  59. ret = ast_wdt_start(dev, 1, flags);
  60. if (ret)
  61. return ret;
  62. while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
  63. ;
  64. return ast_wdt_stop(dev);
  65. }
  66. static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
  67. {
  68. struct ast_wdt_priv *priv = dev_get_priv(dev);
  69. priv->regs = devfdt_get_addr_ptr(dev);
  70. if (IS_ERR(priv->regs))
  71. return PTR_ERR(priv->regs);
  72. return 0;
  73. }
  74. static const struct wdt_ops ast_wdt_ops = {
  75. .start = ast_wdt_start,
  76. .reset = ast_wdt_reset,
  77. .stop = ast_wdt_stop,
  78. .expire_now = ast_wdt_expire_now,
  79. };
  80. static const struct udevice_id ast_wdt_ids[] = {
  81. { .compatible = "aspeed,wdt", .data = WDT_AST2500 },
  82. { .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
  83. { .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
  84. {}
  85. };
  86. static int ast_wdt_probe(struct udevice *dev)
  87. {
  88. debug("%s() wdt%u\n", __func__, dev->seq);
  89. ast_wdt_stop(dev);
  90. return 0;
  91. }
  92. U_BOOT_DRIVER(ast_wdt) = {
  93. .name = "ast_wdt",
  94. .id = UCLASS_WDT,
  95. .of_match = ast_wdt_ids,
  96. .probe = ast_wdt_probe,
  97. .priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
  98. .ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
  99. .ops = &ast_wdt_ops,
  100. };