ac14xx.c 15 KB

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  1. /*
  2. * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
  3. * (C) Copyright 2009 Dave Srl www.dave.eu
  4. * (C) Copyright 2010 ifm ecomatic GmbH
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/bitops.h>
  10. #include <command.h>
  11. #include <asm/io.h>
  12. #include <asm/processor.h>
  13. #include <asm/mpc512x.h>
  14. #include <fdt_support.h>
  15. #ifdef CONFIG_MISC_INIT_R
  16. #include <i2c.h>
  17. #endif
  18. static int mac_diag;
  19. static int gpio_diag;
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static void gpio_configure(void)
  22. {
  23. immap_t *im;
  24. gpio512x_t *gpioregs;
  25. im = (immap_t *) CONFIG_SYS_IMMR;
  26. gpioregs = &im->gpio;
  27. out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
  28. out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
  29. /*
  30. * out_be32(&gpioregs->gpdir, 0xC2293020);
  31. * workaround for a hardware effect: configure direction in pieces,
  32. * setting all outputs at once drops the reset line too low and
  33. * makes us lose the MII connection (breaks ethernet for us)
  34. */
  35. out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
  36. setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
  37. udelay(10);
  38. setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
  39. udelay(10);
  40. setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
  41. udelay(10);
  42. setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
  43. /* to turn from red to yellow when U-Boot runs */
  44. setbits_be32(&gpioregs->gpdat, 0x00002020);
  45. out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
  46. out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
  47. out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
  48. out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
  49. }
  50. /* the physical location of the pins */
  51. #define GPIOKEY_ROW_BITMASK 0x40000000
  52. #define GPIOKEY_ROW_UPPER 0
  53. #define GPIOKEY_ROW_LOWER 1
  54. #define GPIOKEY_COL0_BITMASK 0x20000000
  55. #define GPIOKEY_COL1_BITMASK 0x10000000
  56. #define GPIOKEY_COL2_BITMASK 0x08000000
  57. /* the logical presentation of pressed keys */
  58. #define GPIOKEY_BIT_FNLEFT (1 << 5)
  59. #define GPIOKEY_BIT_FNRIGHT (1 << 4)
  60. #define GPIOKEY_BIT_DIRUP (1 << 3)
  61. #define GPIOKEY_BIT_DIRLEFT (1 << 2)
  62. #define GPIOKEY_BIT_DIRRIGHT (1 << 1)
  63. #define GPIOKEY_BIT_DIRDOWN (1 << 0)
  64. /* the hotkey combination which starts recovery */
  65. #define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
  66. GPIOKEY_BIT_DIRDOWN)
  67. static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
  68. {
  69. if (row)
  70. setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
  71. else
  72. clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
  73. udelay(10);
  74. }
  75. static u32 gpio_querykbd(void)
  76. {
  77. immap_t *im;
  78. gpio512x_t *gpioregs;
  79. u32 keybits;
  80. u32 input;
  81. im = (immap_t *)CONFIG_SYS_IMMR;
  82. gpioregs = &im->gpio;
  83. keybits = 0;
  84. /* query upper row */
  85. gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
  86. input = in_be32(&gpioregs->gpdat);
  87. if ((input & GPIOKEY_COL0_BITMASK) == 0)
  88. keybits |= GPIOKEY_BIT_FNLEFT;
  89. if ((input & GPIOKEY_COL1_BITMASK) == 0)
  90. keybits |= GPIOKEY_BIT_DIRUP;
  91. if ((input & GPIOKEY_COL2_BITMASK) == 0)
  92. keybits |= GPIOKEY_BIT_FNRIGHT;
  93. /* query lower row */
  94. gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
  95. input = in_be32(&gpioregs->gpdat);
  96. if ((input & GPIOKEY_COL0_BITMASK) == 0)
  97. keybits |= GPIOKEY_BIT_DIRLEFT;
  98. if ((input & GPIOKEY_COL1_BITMASK) == 0)
  99. keybits |= GPIOKEY_BIT_DIRRIGHT;
  100. if ((input & GPIOKEY_COL2_BITMASK) == 0)
  101. keybits |= GPIOKEY_BIT_DIRDOWN;
  102. /* return bit pattern for keys */
  103. return keybits;
  104. }
  105. /* excerpt from the recovery's hw_info.h */
  106. struct __attribute__ ((__packed__)) eeprom_layout {
  107. char magic[3]; /** 'ifm' */
  108. u8 len[2]; /** content length without magic/len fields */
  109. u8 version[3]; /** structure version */
  110. u8 type; /** type of PCB */
  111. u8 reserved[0x37]; /** padding up to offset 0x40 */
  112. u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
  113. };
  114. #define HW_COMP_MAINCPU 2
  115. static struct eeprom_layout eeprom_content;
  116. static int eeprom_is_valid;
  117. static int eeprom_version;
  118. #define get_eeprom_field_int(name) ({ \
  119. int value; \
  120. int idx; \
  121. value = 0; \
  122. for (idx = 0; idx < sizeof(name); idx++) { \
  123. value <<= 8; \
  124. value |= name[idx]; \
  125. } \
  126. value; \
  127. })
  128. static int read_eeprom(void)
  129. {
  130. return -ENOSYS;
  131. }
  132. int mac_read_from_eeprom(void)
  133. {
  134. const u8 *mac;
  135. const char *mac_txt;
  136. if (read_eeprom()) {
  137. printf("I2C EEPROM read failed.\n");
  138. return -1;
  139. }
  140. if (!eeprom_is_valid) {
  141. printf("I2C EEPROM content not valid\n");
  142. return -1;
  143. }
  144. mac = NULL;
  145. switch (eeprom_version) {
  146. case 1:
  147. case 2:
  148. mac = (const u8 *)&eeprom_content.macaddress;
  149. break;
  150. }
  151. if (mac && is_valid_ethaddr(mac)) {
  152. eth_setenv_enetaddr("ethaddr", mac);
  153. if (mac_diag) {
  154. mac_txt = getenv("ethaddr");
  155. if (mac_txt)
  156. printf("DIAG: MAC value [%s]\n", mac_txt);
  157. else
  158. printf("DIAG: failed to setup MAC env\n");
  159. }
  160. }
  161. return 0;
  162. }
  163. /*
  164. * BEWARE!
  165. * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
  166. * which the ADS, Aria or PDM360NG boards are using
  167. * (the steps outlined here refer to the Micron datasheet)
  168. */
  169. u32 sdram_init_seq[] = {
  170. /* item 6, at least one NOP after CKE went high */
  171. CONFIG_SYS_DDRCMD_NOP,
  172. CONFIG_SYS_DDRCMD_NOP,
  173. CONFIG_SYS_DDRCMD_NOP,
  174. CONFIG_SYS_DDRCMD_NOP,
  175. CONFIG_SYS_DDRCMD_NOP,
  176. CONFIG_SYS_DDRCMD_NOP,
  177. CONFIG_SYS_DDRCMD_NOP,
  178. CONFIG_SYS_DDRCMD_NOP,
  179. CONFIG_SYS_DDRCMD_NOP,
  180. CONFIG_SYS_DDRCMD_NOP,
  181. /* item 7, precharge all; item 8, tRP (20ns) */
  182. CONFIG_SYS_DDRCMD_PCHG_ALL,
  183. CONFIG_SYS_DDRCMD_NOP,
  184. /* item 9, extended mode register; item 10, tMRD 10ns) */
  185. CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
  186. CONFIG_SYS_DDRCMD_NOP,
  187. /*
  188. * item 11, (base) mode register _with_ reset DLL;
  189. * item 12, tMRD (10ns)
  190. */
  191. CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
  192. CONFIG_SYS_MICRON_BMODE_PARAM,
  193. CONFIG_SYS_DDRCMD_NOP,
  194. /* item 13, precharge all; item 14, tRP (20ns) */
  195. CONFIG_SYS_DDRCMD_PCHG_ALL,
  196. CONFIG_SYS_DDRCMD_NOP,
  197. /*
  198. * item 15, auto refresh (i.e. refresh with CKE held high);
  199. * item 16, tRFC (70ns)
  200. */
  201. CONFIG_SYS_DDRCMD_RFSH,
  202. CONFIG_SYS_DDRCMD_NOP,
  203. CONFIG_SYS_DDRCMD_NOP,
  204. CONFIG_SYS_DDRCMD_NOP,
  205. CONFIG_SYS_DDRCMD_NOP,
  206. CONFIG_SYS_DDRCMD_NOP,
  207. CONFIG_SYS_DDRCMD_NOP,
  208. CONFIG_SYS_DDRCMD_NOP,
  209. CONFIG_SYS_DDRCMD_NOP,
  210. /*
  211. * item 17, auto refresh (i.e. refresh with CKE held high);
  212. * item 18, tRFC (70ns)
  213. */
  214. CONFIG_SYS_DDRCMD_RFSH,
  215. CONFIG_SYS_DDRCMD_NOP,
  216. CONFIG_SYS_DDRCMD_NOP,
  217. CONFIG_SYS_DDRCMD_NOP,
  218. CONFIG_SYS_DDRCMD_NOP,
  219. CONFIG_SYS_DDRCMD_NOP,
  220. CONFIG_SYS_DDRCMD_NOP,
  221. CONFIG_SYS_DDRCMD_NOP,
  222. CONFIG_SYS_DDRCMD_NOP,
  223. /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
  224. CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
  225. CONFIG_SYS_DDRCMD_NOP,
  226. /*
  227. * item 21, "actually done", but make sure 200 DRAM clock cycles
  228. * have passed after DLL reset before READ requests are issued
  229. * (200 cycles at 160MHz -> 1.25 usec)
  230. */
  231. /* EMPTY, optional, we don't do it */
  232. };
  233. int dram_init(void)
  234. {
  235. gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
  236. ARRAY_SIZE(sdram_init_seq));
  237. return 0;
  238. }
  239. int misc_init_r(void)
  240. {
  241. u32 keys;
  242. char *s;
  243. int want_recovery;
  244. /* setup GPIO directions and initial values */
  245. gpio_configure();
  246. /*
  247. * enforce the start of the recovery system when
  248. * - the appropriate keys were pressed
  249. * - "some" external software told us to
  250. * - a previous installation was aborted or has failed
  251. */
  252. want_recovery = 0;
  253. keys = gpio_querykbd();
  254. if (gpio_diag)
  255. printf("GPIO keyboard status [0x%02X]\n", keys);
  256. if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
  257. printf("detected recovery request (keyboard)\n");
  258. want_recovery = 1;
  259. }
  260. s = getenv("want_recovery");
  261. if ((s != NULL) && (*s != '\0')) {
  262. printf("detected recovery request (environment)\n");
  263. want_recovery = 1;
  264. }
  265. s = getenv("install_in_progress");
  266. if ((s != NULL) && (*s != '\0')) {
  267. printf("previous installation has not completed\n");
  268. want_recovery = 1;
  269. }
  270. s = getenv("install_failed");
  271. if ((s != NULL) && (*s != '\0')) {
  272. printf("previous installation has failed\n");
  273. want_recovery = 1;
  274. }
  275. if (want_recovery) {
  276. printf("enforced start of the recovery system\n");
  277. setenv("bootcmd", "run recovery");
  278. }
  279. /*
  280. * boot the recovery system without waiting; boot the
  281. * production system without waiting by default, only
  282. * insert a pause (to provide a chance to get a prompt)
  283. * when GPIO keys were pressed during power on
  284. */
  285. if (want_recovery)
  286. setenv("bootdelay", "0");
  287. else if (!keys)
  288. setenv("bootdelay", "0");
  289. else
  290. setenv("bootdelay", "2");
  291. /* get the ethernet MAC from I2C EEPROM */
  292. mac_read_from_eeprom();
  293. return 0;
  294. }
  295. /* setup specific IO pad configuration */
  296. static iopin_t ioregs_init[] = {
  297. { /* LPC CS3 */
  298. offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
  299. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  300. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  301. },
  302. { /* LPC CS1 */
  303. offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
  304. IO_PIN_OVER_DRVSTR,
  305. IO_PIN_DS(2),
  306. },
  307. { /* LPC CS2 */
  308. offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
  309. IO_PIN_OVER_DRVSTR,
  310. IO_PIN_DS(2),
  311. },
  312. { /* LPC CS4, CS5 */
  313. offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
  314. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  315. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  316. },
  317. { /* SDHC CLK, CMD, D0, D1, D2, D3 */
  318. offsetof(struct ioctrl512x, io_control_pata_ior), 6,
  319. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  320. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  321. },
  322. { /* GPIO keyboard */
  323. offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
  324. IO_PIN_OVER_FMUX,
  325. IO_PIN_FMUX(3),
  326. },
  327. { /* GPIO DN1 PF, LCD power, DN2 PF */
  328. offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
  329. IO_PIN_OVER_FMUX,
  330. IO_PIN_FMUX(3),
  331. },
  332. { /* GPIO reset AS-i */
  333. offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
  334. IO_PIN_OVER_FMUX,
  335. IO_PIN_FMUX(3),
  336. },
  337. { /* GPIO reset safety */
  338. offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
  339. IO_PIN_OVER_FMUX,
  340. IO_PIN_FMUX(3),
  341. },
  342. { /* GPIO reset netX */
  343. offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
  344. IO_PIN_OVER_FMUX,
  345. IO_PIN_FMUX(3),
  346. },
  347. { /* GPIO ma2 en */
  348. offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
  349. IO_PIN_OVER_FMUX,
  350. IO_PIN_FMUX(3),
  351. },
  352. { /* GPIO SD CD, SD WP */
  353. offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
  354. IO_PIN_OVER_FMUX,
  355. IO_PIN_FMUX(3),
  356. },
  357. { /* FEC RX DV */
  358. offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
  359. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  360. IO_PIN_FMUX(2) | IO_PIN_DS(2),
  361. },
  362. { /* GPIO AS-i prog, AS-i done, LCD backlight */
  363. offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
  364. IO_PIN_OVER_FMUX,
  365. IO_PIN_FMUX(3),
  366. },
  367. { /* GPIO AS-i wdg */
  368. offsetof(struct ioctrl512x, io_control_pci_req2), 1,
  369. IO_PIN_OVER_FMUX,
  370. IO_PIN_FMUX(3),
  371. },
  372. { /* GPIO safety wdg */
  373. offsetof(struct ioctrl512x, io_control_pci_req1), 1,
  374. IO_PIN_OVER_FMUX,
  375. IO_PIN_FMUX(3),
  376. },
  377. { /* GPIO netX wdg */
  378. offsetof(struct ioctrl512x, io_control_pci_req0), 1,
  379. IO_PIN_OVER_FMUX,
  380. IO_PIN_FMUX(3),
  381. },
  382. { /* GPIO IRQ powerfail */
  383. offsetof(struct ioctrl512x, io_control_pci_inta), 1,
  384. IO_PIN_OVER_FMUX,
  385. IO_PIN_FMUX(3),
  386. },
  387. { /* GPIO AS-i PWRD */
  388. offsetof(struct ioctrl512x, io_control_pci_frame), 1,
  389. IO_PIN_OVER_FMUX,
  390. IO_PIN_FMUX(3),
  391. },
  392. { /* GPIO LED0, LED1 */
  393. offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
  394. IO_PIN_OVER_FMUX,
  395. IO_PIN_FMUX(3),
  396. },
  397. { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
  398. offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
  399. IO_PIN_OVER_FMUX,
  400. IO_PIN_FMUX(3),
  401. },
  402. { /* DIU clk */
  403. offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
  404. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  405. IO_PIN_FMUX(2) | IO_PIN_DS(2),
  406. },
  407. { /* FEC TX ER, CRS */
  408. offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
  409. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  410. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  411. },
  412. { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
  413. offsetof(struct ioctrl512x, io_control_irq0), 1,
  414. IO_PIN_OVER_FMUX,
  415. IO_PIN_FMUX(3),
  416. },
  417. { /*
  418. * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
  419. * rdx 3-0, mdio, rx clk
  420. */
  421. offsetof(struct ioctrl512x, io_control_psc0_0), 15,
  422. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  423. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  424. },
  425. /* optional: make sure PSC3 remains the serial console */
  426. { /* LPC CS6 */
  427. offsetof(struct ioctrl512x, io_control_psc3_4), 1,
  428. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  429. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  430. },
  431. /* make sure PSC4 remains available for SPI,
  432. *BUT* PSC4_1 is a GPIO kind of SS! */
  433. { /* enforce drive strength on the SPI pin */
  434. offsetof(struct ioctrl512x, io_control_psc4_0), 5,
  435. IO_PIN_OVER_DRVSTR,
  436. IO_PIN_DS(2),
  437. },
  438. {
  439. offsetof(struct ioctrl512x, io_control_psc4_1), 1,
  440. IO_PIN_OVER_FMUX,
  441. IO_PIN_FMUX(3),
  442. },
  443. /* optional: make sure PSC5 remains available for SPI */
  444. { /* enforce drive strength on the SPI pin */
  445. offsetof(struct ioctrl512x, io_control_psc5_0), 5,
  446. IO_PIN_OVER_DRVSTR,
  447. IO_PIN_DS(1),
  448. },
  449. { /* LPC TSIZ1 */
  450. offsetof(struct ioctrl512x, io_control_psc6_0), 1,
  451. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  452. IO_PIN_FMUX(1) | IO_PIN_DS(2),
  453. },
  454. { /* DIU hsync */
  455. offsetof(struct ioctrl512x, io_control_psc6_1), 1,
  456. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  457. IO_PIN_FMUX(2) | IO_PIN_DS(1),
  458. },
  459. { /* DIU vsync */
  460. offsetof(struct ioctrl512x, io_control_psc6_4), 1,
  461. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  462. IO_PIN_FMUX(2) | IO_PIN_DS(1),
  463. },
  464. { /* PSC7, part of DIU RGB */
  465. offsetof(struct ioctrl512x, io_control_psc7_0), 2,
  466. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  467. IO_PIN_FMUX(2) | IO_PIN_DS(1),
  468. },
  469. { /* PSC7, safety UART */
  470. offsetof(struct ioctrl512x, io_control_psc7_2), 2,
  471. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  472. IO_PIN_FMUX(0) | IO_PIN_DS(1),
  473. },
  474. { /* DIU (part of) RGB[] */
  475. offsetof(struct ioctrl512x, io_control_psc8_3), 16,
  476. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  477. IO_PIN_FMUX(2) | IO_PIN_DS(1),
  478. },
  479. { /* DIU data enable */
  480. offsetof(struct ioctrl512x, io_control_psc11_4), 1,
  481. IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
  482. IO_PIN_FMUX(2) | IO_PIN_DS(1),
  483. },
  484. /* reduce LPB drive strength for improved EMI */
  485. { /* LPC OE, LPC RW */
  486. offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
  487. IO_PIN_OVER_DRVSTR,
  488. IO_PIN_DS(2),
  489. },
  490. { /* LPC AX03 through LPC AD00 */
  491. offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
  492. IO_PIN_OVER_DRVSTR,
  493. IO_PIN_DS(2),
  494. },
  495. { /* LPC CS5 */
  496. offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
  497. IO_PIN_OVER_DRVSTR,
  498. IO_PIN_DS(2),
  499. },
  500. { /* SDHC CLK */
  501. offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
  502. IO_PIN_OVER_DRVSTR,
  503. IO_PIN_DS(2),
  504. },
  505. { /* SDHC DATA */
  506. offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
  507. IO_PIN_OVER_DRVSTR,
  508. IO_PIN_DS(2),
  509. },
  510. };
  511. int checkboard(void)
  512. {
  513. puts("Board: ifm AC14xx\n");
  514. /* initialize function mux & slew rate IO inter alia on IO Pins */
  515. iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
  516. return 0;
  517. }
  518. #ifdef CONFIG_OF_BOARD_SETUP
  519. int ft_board_setup(void *blob, bd_t *bd)
  520. {
  521. ft_cpu_setup(blob, bd);
  522. return 0;
  523. }
  524. #endif /* CONFIG_OF_BOARD_SETUP */