canmb.c 4.6 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <mpc5xxx.h>
  12. #include <pci.h>
  13. #if defined(CONFIG_MPC5200_DDR)
  14. #include "mt46v16m16-75.h"
  15. #else
  16. #include "mt48lc16m32s2-75.h"
  17. #endif
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #ifndef CONFIG_SYS_RAMBOOT
  20. static void sdram_start (int hi_addr)
  21. {
  22. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  23. /* unlock mode register */
  24. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  25. __asm__ volatile ("sync");
  26. /* precharge all banks */
  27. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  28. __asm__ volatile ("sync");
  29. #if SDRAM_DDR
  30. /* set mode register: extended mode */
  31. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  32. __asm__ volatile ("sync");
  33. /* set mode register: reset DLL */
  34. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  35. __asm__ volatile ("sync");
  36. #endif
  37. /* precharge all banks */
  38. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  39. __asm__ volatile ("sync");
  40. /* auto refresh */
  41. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  42. __asm__ volatile ("sync");
  43. /* set mode register */
  44. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  45. __asm__ volatile ("sync");
  46. /* normal operation */
  47. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  48. __asm__ volatile ("sync");
  49. }
  50. #endif
  51. /*
  52. * ATTENTION: Although partially referenced dram_init does NOT make real use
  53. * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  54. * is something else than 0x00000000.
  55. */
  56. int dram_init(void)
  57. {
  58. ulong dramsize = 0;
  59. ulong dramsize2 = 0;
  60. #ifndef CONFIG_SYS_RAMBOOT
  61. ulong test1, test2;
  62. /* setup SDRAM chip selects */
  63. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  64. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  65. __asm__ volatile ("sync");
  66. /* setup config registers */
  67. *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  68. *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  69. __asm__ volatile ("sync");
  70. #if SDRAM_DDR
  71. /* set tap delay */
  72. *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
  73. __asm__ volatile ("sync");
  74. #endif
  75. /* find RAM size using SDRAM CS0 only */
  76. sdram_start(0);
  77. test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  78. sdram_start(1);
  79. test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  80. if (test1 > test2) {
  81. sdram_start(0);
  82. dramsize = test1;
  83. } else {
  84. dramsize = test2;
  85. }
  86. /* memory smaller than 1MB is impossible */
  87. if (dramsize < (1 << 20)) {
  88. dramsize = 0;
  89. }
  90. /* set SDRAM CS0 size according to the amount of RAM found */
  91. if (dramsize > 0) {
  92. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
  93. } else {
  94. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
  95. }
  96. /* let SDRAM CS1 start right after CS0 */
  97. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
  98. /* find RAM size using SDRAM CS1 only */
  99. if (!dramsize)
  100. sdram_start(0);
  101. test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
  102. if (!dramsize) {
  103. sdram_start(1);
  104. test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
  105. }
  106. if (test1 > test2) {
  107. sdram_start(0);
  108. dramsize2 = test1;
  109. } else {
  110. dramsize2 = test2;
  111. }
  112. /* memory smaller than 1MB is impossible */
  113. if (dramsize2 < (1 << 20)) {
  114. dramsize2 = 0;
  115. }
  116. /* set SDRAM CS1 size according to the amount of RAM found */
  117. if (dramsize2 > 0) {
  118. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
  119. | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
  120. } else {
  121. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
  122. }
  123. #else /* CONFIG_SYS_RAMBOOT */
  124. /* retrieve size of memory connected to SDRAM CS0 */
  125. dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
  126. if (dramsize >= 0x13) {
  127. dramsize = (1 << (dramsize - 0x13)) << 20;
  128. } else {
  129. dramsize = 0;
  130. }
  131. /* retrieve size of memory connected to SDRAM CS1 */
  132. dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
  133. if (dramsize2 >= 0x13) {
  134. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  135. } else {
  136. dramsize2 = 0;
  137. }
  138. #endif /* CONFIG_SYS_RAMBOOT */
  139. gd->ram_size = dramsize + dramsize2;
  140. return 0;
  141. }
  142. int checkboard (void)
  143. {
  144. puts ("Board: CANMB\n");
  145. return 0;
  146. }
  147. int board_early_init_r (void)
  148. {
  149. *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
  150. *(vu_long *)MPC5XXX_BOOTCS_START =
  151. *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
  152. *(vu_long *)MPC5XXX_BOOTCS_STOP =
  153. *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
  154. return 0;
  155. }