a3m071.c 12 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7. *
  8. * (C) Copyright 2006
  9. * MicroSys GmbH
  10. *
  11. * Copyright 2012-2013 Stefan Roese <sr@denx.de>
  12. *
  13. * SPDX-License-Identifier: GPL-2.0+
  14. */
  15. #include <common.h>
  16. #include <command.h>
  17. #include <mpc5xxx.h>
  18. #include <pci.h>
  19. #include <miiphy.h>
  20. #include <linux/compiler.h>
  21. #include <asm/processor.h>
  22. #include <asm/io.h>
  23. #ifdef CONFIG_A4M2K
  24. #include "is46r16320d.h"
  25. #else
  26. #include "mt46v16m16-75.h"
  27. #endif
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #if !defined(CONFIG_SYS_RAMBOOT) && \
  30. (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
  31. static void sdram_start(int hi_addr)
  32. {
  33. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  34. long control = SDRAM_CONTROL | hi_addr_bit;
  35. /* unlock mode register */
  36. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  37. /* precharge all banks */
  38. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  39. #ifdef SDRAM_DDR
  40. /* set mode register: extended mode */
  41. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
  42. /* set mode register: reset DLL */
  43. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
  44. #endif
  45. /* precharge all banks */
  46. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  47. /* auto refresh */
  48. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  49. /* set mode register */
  50. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  51. /* normal operation */
  52. out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  53. /*
  54. * Wait a short while for the DLL to lock before accessing
  55. * the SDRAM
  56. */
  57. udelay(100);
  58. }
  59. #endif
  60. /*
  61. * ATTENTION: Although partially referenced dram_init does NOT make real use
  62. * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  63. * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  64. */
  65. int dram_init(void)
  66. {
  67. ulong dramsize = 0;
  68. ulong dramsize2 = 0;
  69. uint svr, pvr;
  70. #if !defined(CONFIG_SYS_RAMBOOT) && \
  71. (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
  72. ulong test1, test2;
  73. /* setup SDRAM chip selects */
  74. out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
  75. out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
  76. /* setup config registers */
  77. out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  78. out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  79. #ifdef SDRAM_DDR
  80. /* set tap delay */
  81. out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
  82. #endif
  83. /* find RAM size using SDRAM CS0 only */
  84. sdram_start(0);
  85. test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  86. sdram_start(1);
  87. test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  88. if (test1 > test2) {
  89. sdram_start(0);
  90. dramsize = test1;
  91. } else {
  92. dramsize = test2;
  93. }
  94. /* memory smaller than 1MB is impossible */
  95. if (dramsize < (1 << 20))
  96. dramsize = 0;
  97. /* set SDRAM CS0 size according to the amount of RAM found */
  98. if (dramsize > 0) {
  99. out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
  100. 0x13 + __builtin_ffs(dramsize >> 20) - 1);
  101. } else {
  102. out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
  103. }
  104. #else /* CONFIG_SYS_RAMBOOT */
  105. /* retrieve size of memory connected to SDRAM CS0 */
  106. dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
  107. if (dramsize >= 0x13)
  108. dramsize = (1 << (dramsize - 0x13)) << 20;
  109. else
  110. dramsize = 0;
  111. /* retrieve size of memory connected to SDRAM CS1 */
  112. dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
  113. if (dramsize2 >= 0x13)
  114. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  115. else
  116. dramsize2 = 0;
  117. #endif /* CONFIG_SYS_RAMBOOT */
  118. /*
  119. * On MPC5200B we need to set the special configuration delay in the
  120. * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
  121. * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
  122. *
  123. * "The SDelay should be written to a value of 0x00000004. It is
  124. * required to account for changes caused by normal wafer processing
  125. * parameters."
  126. */
  127. svr = get_svr();
  128. pvr = get_pvr();
  129. if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
  130. out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
  131. gd->ram_size = dramsize + dramsize2;
  132. return 0;
  133. }
  134. static void get_revisions(int *failsavelevel, int *digiboardversion,
  135. int *fpgaversion)
  136. {
  137. struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
  138. u8 val;
  139. /* read digitalboard-version from TMR[2..4] */
  140. val = 0;
  141. val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
  142. val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
  143. val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
  144. *digiboardversion = val;
  145. /*
  146. * A4M2K only supports digiboardversion. No failsavelevel and
  147. * fpgaversion here.
  148. */
  149. #if !defined(CONFIG_A4M2K)
  150. /*
  151. * Figure out failsavelevel
  152. * see ticket dsvk#59
  153. */
  154. *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
  155. if (*digiboardversion == 0) {
  156. *failsavelevel = 1; /* digiboard-version ok */
  157. /* read fpga-version from TMR[5..7] */
  158. val = 0;
  159. val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
  160. val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
  161. val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
  162. *fpgaversion = val;
  163. if (*fpgaversion == 1)
  164. *failsavelevel = 2; /* fpga-version ok */
  165. }
  166. #endif
  167. }
  168. /*
  169. * This function is called from the SPL U-Boot version for
  170. * early init stuff, that needs to be done for OS (e.g. Linux)
  171. * booting. Doing it later in the real U-Boot would not work
  172. * in case that the SPL U-Boot boots Linux directly.
  173. */
  174. void spl_board_init(void)
  175. {
  176. struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
  177. struct mpc5xxx_mmap_ctl *mm =
  178. (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  179. #if defined(CONFIG_A4M2K)
  180. /* enable CS3 and CS5 (FPGA) */
  181. setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
  182. #else
  183. int digiboardversion;
  184. int failsavelevel;
  185. int fpgaversion;
  186. u32 val;
  187. get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
  188. val = in_be32(&mm->ipbi_ws_ctrl);
  189. /* first clear bits 19..21 (CS3...5) */
  190. val &= ~((1 << 19) | (1 << 20) | (1 << 21));
  191. if (failsavelevel == 2) {
  192. /* FPGA ok */
  193. val |= (1 << 19) | (1 << 21);
  194. }
  195. if (failsavelevel >= 1) {
  196. /* at least digiboard-version ok */
  197. val |= (1 << 20);
  198. }
  199. /* And write new value back to register */
  200. out_be32(&mm->ipbi_ws_ctrl, val);
  201. /* Setup pin multiplexing */
  202. if (failsavelevel == 2) {
  203. /* fpga-version ok */
  204. #if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
  205. out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
  206. #endif
  207. } else if (failsavelevel == 1) {
  208. /* digiboard-version ok - fpga not */
  209. #if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
  210. out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
  211. #endif
  212. } else {
  213. /* full failsave-mode */
  214. #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
  215. out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
  216. #endif
  217. }
  218. #endif
  219. /*
  220. * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
  221. * ticket #60
  222. *
  223. * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
  224. * set bit 0(msb) to 1
  225. */
  226. setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
  227. #if defined(CONFIG_A4M2K)
  228. /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
  229. /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
  230. gpio->simple_ddr |= 1 << (31 - 15);
  231. gpio->simple_ddr |= 1 << (31 - 14);
  232. gpio->simple_ddr |= 1 << (31 - 13);
  233. gpio->simple_ddr |= 1 << (31 - 12);
  234. /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
  235. gpio->simple_gpioe |= 1 << (31 - 15);
  236. gpio->simple_gpioe |= 1 << (31 - 14);
  237. gpio->simple_gpioe |= 1 << (31 - 13);
  238. gpio->simple_gpioe |= 1 << (31 - 12);
  239. /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
  240. /* set PSC2[0..2] (STSLED[0..2]) direction to output */
  241. gpio->simple_ddr |= 1 << (31 - 27);
  242. gpio->simple_ddr |= 1 << (31 - 26);
  243. gpio->simple_ddr |= 1 << (31 - 25);
  244. /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
  245. gpio->simple_gpioe |= 1 << (31 - 27);
  246. gpio->simple_gpioe |= 1 << (31 - 26);
  247. gpio->simple_gpioe |= 1 << (31 - 25);
  248. /* Setup PSC6[2] as MRST2 self reset GPIO output */
  249. /* set PSC6[2]/IRDA_TX (MRST2) direction to output */
  250. gpio->simple_ddr |= 1 << (31 - 3);
  251. /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
  252. gpio->simple_ode |= 1 << (31 - 3);
  253. /* set PSC6[2]/IRDA_TX (MRST2) output as default high */
  254. gpio->simple_dvo |= 1 << (31 - 3);
  255. /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
  256. gpio->simple_gpioe |= 1 << (31 - 3);
  257. /* Setup PSC6[3] as HARNSSCD harness code GPIO input */
  258. /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
  259. gpio->simple_ddr |= 0 << (31 - 2);
  260. /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
  261. gpio->simple_gpioe |= 1 << (31 - 2);
  262. #else
  263. /* setup GPIOs for status-leds if needed - see ticket #57 */
  264. if (failsavelevel > 0) {
  265. /* digiboard-version is OK */
  266. /* LED is LOW ACTIVE - so deactivate by set output to 1 */
  267. gpio->simple_dvo |= 1 << (31 - 12);
  268. gpio->simple_dvo |= 1 << (31 - 13);
  269. /* set GPIO direction to output */
  270. gpio->simple_ddr |= 1 << (31 - 12);
  271. gpio->simple_ddr |= 1 << (31 - 13);
  272. /* open drain config is set to "normal output" at reset */
  273. /* gpio->simple_ode &=~ ( 1 << (31-12) ); */
  274. /* gpio->simple_ode &=~ ( 1 << (31-13) ); */
  275. /* enable as GPIO */
  276. gpio->simple_gpioe |= 1 << (31 - 12);
  277. gpio->simple_gpioe |= 1 << (31 - 13);
  278. }
  279. /* setup fpga irq - see ticket #65 */
  280. if (failsavelevel > 1) {
  281. /*
  282. * The main irq initialisation is done in interrupts.c
  283. * mpc5xxx_init_irq
  284. */
  285. struct mpc5xxx_intr *intr =
  286. (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
  287. setbits_be32(&intr->ctrl, 0x08C01801);
  288. /*
  289. * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
  290. * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
  291. */
  292. }
  293. #endif
  294. }
  295. int checkboard(void)
  296. {
  297. int digiboardversion;
  298. int failsavelevel;
  299. int fpgaversion;
  300. get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
  301. #ifdef CONFIG_A4M2K
  302. puts("Board: A4M2K\n");
  303. printf(" digiboard IO version %u\n", digiboardversion);
  304. #else
  305. puts("Board: A3M071\n");
  306. printf("Rev: failsave level %u\n", failsavelevel);
  307. printf(" digiboard IO version %u\n", digiboardversion);
  308. if (failsavelevel > 0) /* only if fpga-version red */
  309. printf(" fpga IO version %u\n", fpgaversion);
  310. #endif
  311. return 0;
  312. }
  313. /* miscellaneous platform dependent initialisations */
  314. int misc_init_r(void)
  315. {
  316. /* adjust flash start and offset to detected values */
  317. gd->bd->bi_flashstart = flash_info[0].start[0];
  318. gd->bd->bi_flashoffset = 0;
  319. /* adjust mapping */
  320. out_be32((void *)MPC5XXX_BOOTCS_START,
  321. START_REG(gd->bd->bi_flashstart));
  322. out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
  323. out_be32((void *)MPC5XXX_BOOTCS_STOP,
  324. STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
  325. out_be32((void *)MPC5XXX_CS0_STOP,
  326. STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
  327. return 0;
  328. }
  329. #ifdef CONFIG_OF_BOARD_SETUP
  330. int ft_board_setup(void *blob, bd_t *bd)
  331. {
  332. ft_cpu_setup(blob, bd);
  333. return 0;
  334. }
  335. #endif /* CONFIG_OF_BOARD_SETUP */
  336. #ifdef CONFIG_SPL_OS_BOOT
  337. /*
  338. * A3M071 specific implementation of spl_start_uboot()
  339. *
  340. * RETURN
  341. * 0 if booting into OS is selected (default)
  342. * 1 if booting into U-Boot is selected
  343. */
  344. int spl_start_uboot(void)
  345. {
  346. char s[8];
  347. env_init();
  348. getenv_f("boot_os", s, sizeof(s));
  349. if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
  350. *s == 't' || *s == 'T'))
  351. return 0;
  352. return 1;
  353. }
  354. #endif
  355. #if defined(CONFIG_HW_WATCHDOG)
  356. static int watchdog_toggle;
  357. void hw_watchdog_reset(void)
  358. {
  359. int val;
  360. /*
  361. * Check if watchdog is enabled via user command
  362. */
  363. if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
  364. /* Set direction to output */
  365. setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
  366. /*
  367. * Toggle watchdog output
  368. */
  369. val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
  370. CONFIG_WDOG_GPIO_PIN);
  371. if (val) {
  372. clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
  373. CONFIG_WDOG_GPIO_PIN);
  374. } else {
  375. setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
  376. CONFIG_WDOG_GPIO_PIN);
  377. }
  378. }
  379. }
  380. int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  381. {
  382. if (argc != 2)
  383. goto usage;
  384. if (strncmp(argv[1], "on", 2) == 0)
  385. watchdog_toggle = 1;
  386. else if (strncmp(argv[1], "off", 3) == 0)
  387. watchdog_toggle = 0;
  388. else
  389. goto usage;
  390. return 0;
  391. usage:
  392. printf("Usage: wdogtoggle %s\n", cmdtp->usage);
  393. return 1;
  394. }
  395. U_BOOT_CMD(
  396. wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
  397. "toggle GPIO pin to service watchdog",
  398. "[on/off] - Switch watchdog toggling via GPIO pin on/off"
  399. );
  400. #endif