interrupts.c 7.9 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Detlev Zundel, DENX Software Engineering, dzu@denx.de
  4. *
  5. * (C) Copyright -2003
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * (C) Copyright 2001
  9. * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. /* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the
  14. * Linux 2.6 source with the following copyright.
  15. *
  16. * Based on (well, mostly copied from) the code from the 2.4 kernel by
  17. * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
  18. *
  19. * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  20. * Copyright (C) 2003 Montavista Software, Inc
  21. */
  22. #include <common.h>
  23. #include <asm/processor.h>
  24. #include <asm/io.h>
  25. #include <command.h>
  26. struct irq_action {
  27. interrupt_handler_t *handler;
  28. void *arg;
  29. ulong count;
  30. };
  31. static struct irq_action irq_handlers[NR_IRQS];
  32. static struct mpc5xxx_intr *intr;
  33. static struct mpc5xxx_sdma *sdma;
  34. static void mpc5xxx_ic_disable(unsigned int irq)
  35. {
  36. u32 val;
  37. if (irq == MPC5XXX_IRQ0) {
  38. val = in_be32(&intr->ctrl);
  39. val &= ~(1 << 11);
  40. out_be32(&intr->ctrl, val);
  41. } else if (irq < MPC5XXX_IRQ1) {
  42. BUG();
  43. } else if (irq <= MPC5XXX_IRQ3) {
  44. val = in_be32(&intr->ctrl);
  45. val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
  46. out_be32(&intr->ctrl, val);
  47. } else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
  48. val = in_be32(&intr->main_mask);
  49. val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
  50. out_be32(&intr->main_mask, val);
  51. } else if (irq < MPC5XXX_PERP_IRQ_BASE) {
  52. val = in_be32(&sdma->IntMask);
  53. val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
  54. out_be32(&sdma->IntMask, val);
  55. } else {
  56. val = in_be32(&intr->per_mask);
  57. val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
  58. out_be32(&intr->per_mask, val);
  59. }
  60. }
  61. static void mpc5xxx_ic_enable(unsigned int irq)
  62. {
  63. u32 val;
  64. if (irq == MPC5XXX_IRQ0) {
  65. val = in_be32(&intr->ctrl);
  66. val |= 1 << 11;
  67. out_be32(&intr->ctrl, val);
  68. } else if (irq < MPC5XXX_IRQ1) {
  69. BUG();
  70. } else if (irq <= MPC5XXX_IRQ3) {
  71. val = in_be32(&intr->ctrl);
  72. val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
  73. out_be32(&intr->ctrl, val);
  74. } else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
  75. val = in_be32(&intr->main_mask);
  76. val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
  77. out_be32(&intr->main_mask, val);
  78. } else if (irq < MPC5XXX_PERP_IRQ_BASE) {
  79. val = in_be32(&sdma->IntMask);
  80. val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
  81. out_be32(&sdma->IntMask, val);
  82. } else {
  83. val = in_be32(&intr->per_mask);
  84. val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
  85. out_be32(&intr->per_mask, val);
  86. }
  87. }
  88. static void mpc5xxx_ic_ack(unsigned int irq)
  89. {
  90. u32 val;
  91. /*
  92. * Only some irqs are reset here, others in interrupting hardware.
  93. */
  94. switch (irq) {
  95. case MPC5XXX_IRQ0:
  96. val = in_be32(&intr->ctrl);
  97. val |= 0x08000000;
  98. out_be32(&intr->ctrl, val);
  99. break;
  100. case MPC5XXX_CCS_IRQ:
  101. val = in_be32(&intr->enc_status);
  102. val |= 0x00000400;
  103. out_be32(&intr->enc_status, val);
  104. break;
  105. case MPC5XXX_IRQ1:
  106. val = in_be32(&intr->ctrl);
  107. val |= 0x04000000;
  108. out_be32(&intr->ctrl, val);
  109. break;
  110. case MPC5XXX_IRQ2:
  111. val = in_be32(&intr->ctrl);
  112. val |= 0x02000000;
  113. out_be32(&intr->ctrl, val);
  114. break;
  115. case MPC5XXX_IRQ3:
  116. val = in_be32(&intr->ctrl);
  117. val |= 0x01000000;
  118. out_be32(&intr->ctrl, val);
  119. break;
  120. default:
  121. if (irq >= MPC5XXX_SDMA_IRQ_BASE
  122. && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
  123. out_be32(&sdma->IntPend,
  124. 1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
  125. }
  126. break;
  127. }
  128. }
  129. static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
  130. {
  131. mpc5xxx_ic_disable(irq);
  132. mpc5xxx_ic_ack(irq);
  133. }
  134. static void mpc5xxx_ic_end(unsigned int irq)
  135. {
  136. mpc5xxx_ic_enable(irq);
  137. }
  138. void mpc5xxx_init_irq(void)
  139. {
  140. u32 intr_ctrl;
  141. /* Remap the necessary zones */
  142. intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
  143. sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
  144. /* Disable all interrupt sources. */
  145. out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
  146. out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
  147. out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
  148. out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
  149. intr_ctrl = in_be32(&intr->ctrl);
  150. intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
  151. 0x00ff0000 | /* IRQ 0-3 level sensitive low active */
  152. 0x00001000 | /* MEE master external enable */
  153. 0x00000000 | /* 0 means disable IRQ 0-3 */
  154. 0x00000001; /* CEb route critical normally */
  155. out_be32(&intr->ctrl, intr_ctrl);
  156. /* Zero a bunch of the priority settings. */
  157. out_be32(&intr->per_pri1, 0);
  158. out_be32(&intr->per_pri2, 0);
  159. out_be32(&intr->per_pri3, 0);
  160. out_be32(&intr->main_pri1, 0);
  161. out_be32(&intr->main_pri2, 0);
  162. }
  163. int mpc5xxx_get_irq(struct pt_regs *regs)
  164. {
  165. u32 status;
  166. int irq = -1;
  167. status = in_be32(&intr->enc_status);
  168. if (status & 0x00000400) { /* critical */
  169. irq = (status >> 8) & 0x3;
  170. if (irq == 2) /* high priority peripheral */
  171. goto peripheral;
  172. irq += MPC5XXX_CRIT_IRQ_BASE;
  173. } else if (status & 0x00200000) { /* main */
  174. irq = (status >> 16) & 0x1f;
  175. if (irq == 4) /* low priority peripheral */
  176. goto peripheral;
  177. irq += MPC5XXX_MAIN_IRQ_BASE;
  178. } else if (status & 0x20000000) { /* peripheral */
  179. peripheral:
  180. irq = (status >> 24) & 0x1f;
  181. if (irq == 0) { /* bestcomm */
  182. status = in_be32(&sdma->IntPend);
  183. irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
  184. } else
  185. irq += MPC5XXX_PERP_IRQ_BASE;
  186. }
  187. return irq;
  188. }
  189. /****************************************************************************/
  190. int interrupt_init_cpu(ulong * decrementer_count)
  191. {
  192. *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  193. mpc5xxx_init_irq();
  194. return (0);
  195. }
  196. /****************************************************************************/
  197. /*
  198. * Handle external interrupts
  199. */
  200. void external_interrupt(struct pt_regs *regs)
  201. {
  202. int irq, unmask = 1;
  203. irq = mpc5xxx_get_irq(regs);
  204. mpc5xxx_ic_disable_and_ack(irq);
  205. enable_interrupts();
  206. if (irq_handlers[irq].handler != NULL)
  207. (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
  208. else {
  209. printf("\nBogus External Interrupt IRQ %d\n", irq);
  210. /*
  211. * turn off the bogus interrupt, otherwise it
  212. * might repeat forever
  213. */
  214. unmask = 0;
  215. }
  216. if (unmask)
  217. mpc5xxx_ic_end(irq);
  218. }
  219. void timer_interrupt_cpu(struct pt_regs *regs)
  220. {
  221. /* nothing to do here */
  222. return;
  223. }
  224. /****************************************************************************/
  225. /*
  226. * Install and free a interrupt handler.
  227. */
  228. void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
  229. {
  230. if (irq < 0 || irq >= NR_IRQS) {
  231. printf("irq_install_handler: bad irq number %d\n", irq);
  232. return;
  233. }
  234. if (irq_handlers[irq].handler != NULL)
  235. printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
  236. (ulong) handler, (ulong) irq_handlers[irq].handler);
  237. irq_handlers[irq].handler = handler;
  238. irq_handlers[irq].arg = arg;
  239. mpc5xxx_ic_enable(irq);
  240. }
  241. void irq_free_handler(int irq)
  242. {
  243. if (irq < 0 || irq >= NR_IRQS) {
  244. printf("irq_free_handler: bad irq number %d\n", irq);
  245. return;
  246. }
  247. mpc5xxx_ic_disable(irq);
  248. irq_handlers[irq].handler = NULL;
  249. irq_handlers[irq].arg = NULL;
  250. }
  251. /****************************************************************************/
  252. #if defined(CONFIG_CMD_IRQ)
  253. void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
  254. {
  255. int irq, re_enable;
  256. u32 intr_ctrl;
  257. char *irq_config[] = { "level sensitive, active high",
  258. "edge sensitive, rising active edge",
  259. "edge sensitive, falling active edge",
  260. "level sensitive, active low"
  261. };
  262. re_enable = disable_interrupts();
  263. intr_ctrl = in_be32(&intr->ctrl);
  264. printf("Interrupt configuration:\n");
  265. for (irq = 0; irq <= 3; irq++) {
  266. printf("IRQ%d: %s\n", irq,
  267. irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
  268. }
  269. puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
  270. for (irq = 0; irq < NR_IRQS; irq++)
  271. if (irq_handlers[irq].handler != NULL)
  272. printf("%02d %08lx %08lx %ld\n", irq,
  273. (ulong) irq_handlers[irq].handler,
  274. (ulong) irq_handlers[irq].arg,
  275. irq_handlers[irq].count);
  276. if (re_enable)
  277. enable_interrupts();
  278. }
  279. #endif