pci.c 5.2 KB

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  1. /*
  2. * Copyright (C) 2009-2010 DENX Software Engineering <wd@denx.de>
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/mmu.h>
  10. #include <asm/global_data.h>
  11. #include <pci.h>
  12. #if defined(CONFIG_OF_LIBFDT)
  13. #include <libfdt.h>
  14. #include <fdt_support.h>
  15. #endif
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* System RAM mapped to PCI space */
  18. #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
  19. #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  20. static struct pci_controller pci_hose;
  21. /**************************************************************************
  22. * pci_init_board()
  23. *
  24. */
  25. void
  26. pci_init_board(void)
  27. {
  28. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  29. volatile law512x_t *pci_law;
  30. volatile pot512x_t *pci_pot;
  31. volatile pcictrl512x_t *pci_ctrl;
  32. u16 reg16;
  33. u32 reg32;
  34. u32 dev;
  35. int i;
  36. struct pci_controller *hose;
  37. /* Set PCI divider for 33MHz */
  38. reg32 = in_be32(&im->clk.scfr[0]);
  39. reg32 &= ~(SCFR1_PCI_DIV_MASK);
  40. reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
  41. out_be32(&im->clk.scfr[0], reg32);
  42. clrsetbits_be32(&im->clk.scfr[0],
  43. SCFR1_PCI_DIV_MASK,
  44. SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
  45. );
  46. pci_law = im->sysconf.pcilaw;
  47. pci_pot = im->ios.pot;
  48. pci_ctrl = &im->pci_ctrl;
  49. hose = &pci_hose;
  50. /*
  51. * Release PCI RST Output signal
  52. */
  53. out_be32(&pci_ctrl->gcr, 0);
  54. udelay(2000);
  55. out_be32(&pci_ctrl->gcr, 1);
  56. /* We need to wait at least a 1sec based on PCI specs */
  57. for (i = 0; i < 1000; i++)
  58. udelay(1000);
  59. /*
  60. * Configure PCI Local Access Windows
  61. */
  62. out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
  63. out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
  64. out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
  65. out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
  66. /*
  67. * Configure PCI Outbound Translation Windows
  68. */
  69. /* PCI mem space - prefetch */
  70. out_be32(&pci_pot[0].potar,
  71. (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
  72. out_be32(&pci_pot[0].pobar,
  73. (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
  74. out_be32(&pci_pot[0].pocmr,
  75. POCMR_EN | POCMR_PRE | POCMR_CM_256M);
  76. /* PCI IO space */
  77. out_be32(&pci_pot[1].potar,
  78. (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
  79. out_be32(&pci_pot[1].pobar,
  80. (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
  81. out_be32(&pci_pot[1].pocmr,
  82. POCMR_EN | POCMR_IO | POCMR_CM_16M);
  83. /* PCI mmio - non-prefetch mem space */
  84. out_be32(&pci_pot[2].potar,
  85. (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
  86. out_be32(&pci_pot[2].pobar,
  87. (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
  88. out_be32(&pci_pot[2].pocmr,
  89. POCMR_EN | POCMR_CM_256M);
  90. /*
  91. * Configure PCI Inbound Translation Windows
  92. */
  93. /* we need RAM mapped to PCI space for the devices to
  94. * access main memory */
  95. out_be32(&pci_ctrl[0].pitar1, 0x0);
  96. out_be32(&pci_ctrl[0].pibar1, 0x0);
  97. out_be32(&pci_ctrl[0].piebar1, 0x0);
  98. out_be32(&pci_ctrl[0].piwar1,
  99. PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
  100. PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
  101. hose->first_busno = 0;
  102. hose->last_busno = 0xff;
  103. /* PCI memory prefetch space */
  104. pci_set_region(hose->regions + 0,
  105. CONFIG_SYS_PCI_MEM_BASE,
  106. CONFIG_SYS_PCI_MEM_PHYS,
  107. CONFIG_SYS_PCI_MEM_SIZE,
  108. PCI_REGION_MEM|PCI_REGION_PREFETCH);
  109. /* PCI memory space */
  110. pci_set_region(hose->regions + 1,
  111. CONFIG_SYS_PCI_MMIO_BASE,
  112. CONFIG_SYS_PCI_MMIO_PHYS,
  113. CONFIG_SYS_PCI_MMIO_SIZE,
  114. PCI_REGION_MEM);
  115. /* PCI IO space */
  116. pci_set_region(hose->regions + 2,
  117. CONFIG_SYS_PCI_IO_BASE,
  118. CONFIG_SYS_PCI_IO_PHYS,
  119. CONFIG_SYS_PCI_IO_SIZE,
  120. PCI_REGION_IO);
  121. /* System memory space */
  122. pci_set_region(hose->regions + 3,
  123. CONFIG_PCI_SYS_MEM_BUS,
  124. CONFIG_PCI_SYS_MEM_PHYS,
  125. gd->ram_size,
  126. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  127. hose->region_count = 4;
  128. pci_setup_indirect(hose,
  129. (CONFIG_SYS_IMMR + 0x8300),
  130. (CONFIG_SYS_IMMR + 0x8304));
  131. pci_register_hose(hose);
  132. /*
  133. * Write to Command register
  134. */
  135. reg16 = 0xff;
  136. dev = PCI_BDF(hose->first_busno, 0, 0);
  137. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
  138. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  139. pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  140. /*
  141. * Clear non-reserved bits in status register.
  142. */
  143. pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  144. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  145. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  146. #ifdef CONFIG_PCI_SCAN_SHOW
  147. printf("PCI: Bus Dev VenId DevId Class Int\n");
  148. #endif
  149. /*
  150. * Hose scan.
  151. */
  152. hose->last_busno = pci_hose_scan(hose);
  153. }
  154. #if defined(CONFIG_OF_LIBFDT)
  155. void ft_pci_setup(void *blob, bd_t *bd)
  156. {
  157. int nodeoffset;
  158. int tmp[2];
  159. const char *path;
  160. nodeoffset = fdt_path_offset(blob, "/aliases");
  161. if (nodeoffset >= 0) {
  162. path = fdt_getprop(blob, nodeoffset, "pci", NULL);
  163. if (path) {
  164. tmp[0] = cpu_to_be32(pci_hose.first_busno);
  165. tmp[1] = cpu_to_be32(pci_hose.last_busno);
  166. do_fixup_by_path(blob, path, "bus-range",
  167. &tmp, sizeof(tmp), 1);
  168. tmp[0] = cpu_to_be32(gd->pci_clk);
  169. do_fixup_by_path(blob, path, "clock-frequency",
  170. &tmp, sizeof(tmp[0]), 1);
  171. }
  172. }
  173. }
  174. #endif /* CONFIG_OF_LIBFDT */