cpu.c 4.0 KB

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  1. /*
  2. * (C) Copyright 2007-2010 DENX Software Engineering
  3. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * CPU specific code for the MPC512x family.
  9. *
  10. * Derived from the MPC83xx code.
  11. */
  12. #include <common.h>
  13. #include <command.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <asm/processor.h>
  17. #include <asm/io.h>
  18. #if defined(CONFIG_OF_LIBFDT)
  19. #include <fdt_support.h>
  20. #endif
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int checkcpu (void)
  23. {
  24. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  25. ulong clock = gd->cpu_clk;
  26. u32 pvr = get_pvr ();
  27. u32 spridr = in_be32(&immr->sysconf.spridr);
  28. char buf1[32], buf2[32];
  29. puts ("CPU: ");
  30. switch (spridr & 0xffff0000) {
  31. case SPR_5121E:
  32. puts ("MPC5121e ");
  33. break;
  34. default:
  35. printf ("Unknown part ID %08x ", spridr & 0xffff0000);
  36. }
  37. printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
  38. switch (pvr & 0xffff0000) {
  39. case PVR_E300C4:
  40. puts ("e300c4 ");
  41. break;
  42. default:
  43. puts ("unknown ");
  44. }
  45. printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
  46. strmhz(buf1, clock),
  47. strmhz(buf2, gd->arch.csb_clk),
  48. gd->arch.reset_status & 0xffff);
  49. return 0;
  50. }
  51. int
  52. do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  53. {
  54. ulong msr;
  55. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  56. /* Interrupts and MMU off */
  57. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  58. msr &= ~( MSR_EE | MSR_IR | MSR_DR);
  59. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  60. /*
  61. * Enable Reset Control Reg - "RSTE" is the magic word that let us go
  62. */
  63. out_be32(&immap->reset.rpr, 0x52535445);
  64. /* Verify Reset Control Reg is enabled */
  65. while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
  66. ;
  67. printf ("Resetting the board.\n");
  68. udelay(200);
  69. /* Perform reset */
  70. out_be32(&immap->reset.rcr, RCR_SWHR);
  71. /* Unreached... */
  72. return 1;
  73. }
  74. /*
  75. * Get timebase clock frequency (like cpu_clk in Hz)
  76. */
  77. unsigned long get_tbclk (void)
  78. {
  79. return (gd->bus_clk + 3L) / 4L;
  80. }
  81. #if defined(CONFIG_WATCHDOG)
  82. void watchdog_reset (void)
  83. {
  84. int re_enable = disable_interrupts ();
  85. /* Reset watchdog */
  86. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  87. out_be32(&immr->wdt.swsrr, 0x556c);
  88. out_be32(&immr->wdt.swsrr, 0xaa39);
  89. if (re_enable)
  90. enable_interrupts ();
  91. }
  92. #endif
  93. #ifdef CONFIG_OF_LIBFDT
  94. #ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
  95. /*
  96. * fdt setup for old device trees
  97. * fix up
  98. * cpu clocks
  99. * soc clocks
  100. * ethernet addresses
  101. */
  102. static void old_ft_cpu_setup(void *blob, bd_t *bd)
  103. {
  104. /*
  105. * avoid fixing up by path because that
  106. * produces scary error messages
  107. */
  108. uchar enetaddr[6];
  109. /*
  110. * old device trees have ethernet nodes with
  111. * device_type = "network"
  112. */
  113. eth_getenv_enetaddr("ethaddr", enetaddr);
  114. do_fixup_by_prop(blob, "device_type", "network", 8,
  115. "local-mac-address", enetaddr, 6, 0);
  116. do_fixup_by_prop(blob, "device_type", "network", 8,
  117. "address", enetaddr, 6, 0);
  118. /*
  119. * old device trees have soc nodes with
  120. * device_type = "soc"
  121. */
  122. do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
  123. "bus-frequency", bd->bi_ipsfreq, 0);
  124. }
  125. #endif
  126. static void ft_clock_setup(void *blob, bd_t *bd)
  127. {
  128. char *cpu_path = "/cpus/" OF_CPU;
  129. /*
  130. * fixup cpu clocks using path
  131. */
  132. do_fixup_by_path_u32(blob, cpu_path,
  133. "timebase-frequency", OF_TBCLK, 1);
  134. do_fixup_by_path_u32(blob, cpu_path,
  135. "bus-frequency", bd->bi_busfreq, 1);
  136. do_fixup_by_path_u32(blob, cpu_path,
  137. "clock-frequency", bd->bi_intfreq, 1);
  138. /*
  139. * fixup soc clocks using compatible
  140. */
  141. do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
  142. "bus-frequency", bd->bi_ipsfreq, 1);
  143. }
  144. void ft_cpu_setup(void *blob, bd_t *bd)
  145. {
  146. #ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
  147. old_ft_cpu_setup(blob, bd);
  148. #endif
  149. ft_clock_setup(blob, bd);
  150. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  151. }
  152. #endif
  153. #ifdef CONFIG_MPC512x_FEC
  154. /* Default initializations for FEC controllers. To override,
  155. * create a board-specific function called:
  156. * int board_eth_init(bd_t *bis)
  157. */
  158. int cpu_eth_init(bd_t *bis)
  159. {
  160. return mpc512x_fec_initialize(bis);
  161. }
  162. #endif