misc_s10.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <altera.h>
  7. #include <common.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <miiphy.h>
  11. #include <netdev.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/reset_manager.h>
  14. #include <asm/arch/system_manager.h>
  15. #include <asm/arch/misc.h>
  16. #include <asm/pl310.h>
  17. #include <linux/libfdt.h>
  18. #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static struct socfpga_system_manager *sysmgr_regs =
  21. (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  22. /*
  23. * FPGA programming support for SoC FPGA Stratix 10
  24. */
  25. static Altera_desc altera_fpga[] = {
  26. {
  27. /* Family */
  28. Intel_FPGA_Stratix10,
  29. /* Interface type */
  30. secure_device_manager_mailbox,
  31. /* No limitation as additional data will be ignored */
  32. -1,
  33. /* No device function table */
  34. NULL,
  35. /* Base interface address specified in driver */
  36. NULL,
  37. /* No cookie implementation */
  38. 0
  39. },
  40. };
  41. /*
  42. * DesignWare Ethernet initialization
  43. */
  44. #ifdef CONFIG_ETH_DESIGNWARE
  45. static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
  46. {
  47. u32 modereg;
  48. if (!phymode)
  49. return -EINVAL;
  50. if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
  51. !strcmp(phymode, "sgmii"))
  52. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  53. else if (!strcmp(phymode, "rgmii"))
  54. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  55. else if (!strcmp(phymode, "rmii"))
  56. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  57. else
  58. return -EINVAL;
  59. clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
  60. SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
  61. modereg);
  62. return 0;
  63. }
  64. static int socfpga_set_phymode(void)
  65. {
  66. const void *fdt = gd->fdt_blob;
  67. struct fdtdec_phandle_args args;
  68. const char *phy_mode;
  69. u32 gmac_index;
  70. int nodes[3]; /* Max. 3 GMACs */
  71. int ret, count;
  72. int i, node;
  73. count = fdtdec_find_aliases_for_id(fdt, "ethernet",
  74. COMPAT_ALTERA_SOCFPGA_DWMAC,
  75. nodes, ARRAY_SIZE(nodes));
  76. for (i = 0; i < count; i++) {
  77. node = nodes[i];
  78. if (node <= 0)
  79. continue;
  80. ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
  81. "#reset-cells", 1, 0,
  82. &args);
  83. if (ret || args.args_count != 1) {
  84. debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
  85. continue;
  86. }
  87. gmac_index = args.args[0] - EMAC0_RESET;
  88. phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
  89. ret = socfpga_phymode_setup(gmac_index, phy_mode);
  90. if (ret) {
  91. debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
  92. continue;
  93. }
  94. }
  95. return 0;
  96. }
  97. #else
  98. static int socfpga_set_phymode(void)
  99. {
  100. return 0;
  101. };
  102. #endif
  103. /*
  104. * Print CPU information
  105. */
  106. #if defined(CONFIG_DISPLAY_CPUINFO)
  107. int print_cpuinfo(void)
  108. {
  109. puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
  110. return 0;
  111. }
  112. #endif
  113. #ifdef CONFIG_ARCH_MISC_INIT
  114. int arch_misc_init(void)
  115. {
  116. char qspi_string[13];
  117. sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
  118. env_set("qspi_clock", qspi_string);
  119. socfpga_set_phymode();
  120. return 0;
  121. }
  122. #endif
  123. int arch_early_init_r(void)
  124. {
  125. socfpga_fpga_add(&altera_fpga[0]);
  126. return 0;
  127. }
  128. void do_bridge_reset(int enable)
  129. {
  130. socfpga_bridges_reset(enable);
  131. }