misc_arria10.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2017 Intel Corporation
  4. */
  5. #include <altera.h>
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <miiphy.h>
  10. #include <netdev.h>
  11. #include <ns16550.h>
  12. #include <watchdog.h>
  13. #include <asm/arch/misc.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <asm/arch/reset_manager_arria10.h>
  17. #include <asm/arch/sdram_arria10.h>
  18. #include <asm/arch/system_manager.h>
  19. #include <asm/arch/nic301.h>
  20. #include <asm/io.h>
  21. #include <asm/pl310.h>
  22. #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
  23. #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
  24. #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
  25. #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
  26. #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
  27. #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
  28. static struct socfpga_system_manager *sysmgr_regs =
  29. (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  30. /*
  31. * FPGA programming support for SoC FPGA Arria 10
  32. */
  33. static Altera_desc altera_fpga[] = {
  34. {
  35. /* Family */
  36. Altera_SoCFPGA,
  37. /* Interface type */
  38. fast_passive_parallel,
  39. /* No limitation as additional data will be ignored */
  40. -1,
  41. /* No device function table */
  42. NULL,
  43. /* Base interface address specified in driver */
  44. NULL,
  45. /* No cookie implementation */
  46. 0
  47. },
  48. };
  49. #if defined(CONFIG_SPL_BUILD)
  50. static struct pl310_regs *const pl310 =
  51. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  52. static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
  53. (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
  54. /*
  55. + * This function initializes security policies to be consistent across
  56. + * all logic units in the Arria 10.
  57. + *
  58. + * The idea is to set all security policies to be normal, nonsecure
  59. + * for all units.
  60. + */
  61. void socfpga_init_security_policies(void)
  62. {
  63. /* Put OCRAM in non-secure */
  64. writel(0x003f0000, &noc_fw_ocram_base->region0);
  65. writel(0x1, &noc_fw_ocram_base->enable);
  66. /* Put DDR in non-secure */
  67. writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
  68. writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
  69. /* Enable priviledged and non-priviledged access to L4 peripherals */
  70. writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
  71. /* Enable secure and non-secure transactions to bridges */
  72. writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
  73. writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
  74. writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
  75. }
  76. void socfpga_sdram_remap_zero(void)
  77. {
  78. /* Configure the L2 controller to make SDRAM start at 0 */
  79. writel(0x1, &pl310->pl310_addr_filter_start);
  80. }
  81. #endif
  82. int arch_early_init_r(void)
  83. {
  84. /* Add device descriptor to FPGA device table */
  85. socfpga_fpga_add(&altera_fpga[0]);
  86. return 0;
  87. }
  88. /*
  89. * Print CPU information
  90. */
  91. #if defined(CONFIG_DISPLAY_CPUINFO)
  92. int print_cpuinfo(void)
  93. {
  94. const u32 bsel =
  95. SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
  96. puts("CPU: Altera SoCFPGA Arria 10\n");
  97. printf("BOOT: %s\n", bsel_str[bsel].name);
  98. return 0;
  99. }
  100. #endif
  101. void do_bridge_reset(int enable)
  102. {
  103. if (enable)
  104. socfpga_reset_deassert_bridges_handoff();
  105. else
  106. socfpga_bridges_reset();
  107. }