mv_eth.c 102 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Ingo Assmus <ingo.assmus@keymile.com>
  4. *
  5. * based on - Driver for MV64360X ethernet ports
  6. * Copyright (C) 2002 rabeeh@galileo.co.il
  7. *
  8. * SPDX-License-Identifier: GPL-2.0
  9. */
  10. /*
  11. * mv_eth.c - header file for the polled mode GT ethernet driver
  12. */
  13. #include <common.h>
  14. #include <net.h>
  15. #include <malloc.h>
  16. #include "mv_eth.h"
  17. /* enable Debug outputs */
  18. #undef DEBUG_MV_ETH
  19. #ifdef DEBUG_MV_ETH
  20. #define DEBUG
  21. #define DP(x) x
  22. #else
  23. #define DP(x)
  24. #endif
  25. #undef MV64360_CHECKSUM_OFFLOAD
  26. /*************************************************************************
  27. **************************************************************************
  28. **************************************************************************
  29. * The first part is the high level driver of the gigE ethernet ports. *
  30. **************************************************************************
  31. **************************************************************************
  32. *************************************************************************/
  33. /* Definition for configuring driver */
  34. /* #define UPDATE_STATS_BY_SOFTWARE */
  35. #undef MV64360_RX_QUEUE_FILL_ON_TASK
  36. /* Constants */
  37. #define MAGIC_ETH_RUNNING 8031971
  38. #define MV64360_INTERNAL_SRAM_SIZE _256K
  39. #define EXTRA_BYTES 32
  40. #define WRAP ETH_HLEN + 2 + 4 + 16
  41. #define BUFFER_MTU dev->mtu + WRAP
  42. #define INT_CAUSE_UNMASK_ALL 0x0007ffff
  43. #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
  44. #ifdef MV64360_RX_FILL_ON_TASK
  45. #define INT_CAUSE_MASK_ALL 0x00000000
  46. #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
  47. #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
  48. #endif
  49. /* Read/Write to/from MV64360 internal registers */
  50. #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
  51. #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
  52. #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
  53. #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
  54. /* Static function declarations */
  55. static int mv64360_eth_real_open (struct eth_device *eth);
  56. static int mv64360_eth_real_stop (struct eth_device *eth);
  57. static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
  58. *dev);
  59. static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
  60. static void mv64360_eth_update_stat (struct eth_device *dev);
  61. bool db64360_eth_start (struct eth_device *eth);
  62. unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
  63. unsigned int mib_offset);
  64. int mv64360_eth_receive (struct eth_device *dev);
  65. int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
  66. #ifndef UPDATE_STATS_BY_SOFTWARE
  67. static void mv64360_eth_print_stat (struct eth_device *dev);
  68. #endif
  69. extern unsigned int INTERNAL_REG_BASE_ADDR;
  70. /*************************************************
  71. *Helper functions - used inside the driver only *
  72. *************************************************/
  73. #ifdef DEBUG_MV_ETH
  74. void print_globals (struct eth_device *dev)
  75. {
  76. printf ("Ethernet PRINT_Globals-Debug function\n");
  77. printf ("Base Address for ETH_PORT_INFO: %08x\n",
  78. (unsigned int) dev->priv);
  79. printf ("Base Address for mv64360_eth_priv: %08x\n",
  80. (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
  81. port_private));
  82. printf ("GT Internal Base Address: %08x\n",
  83. INTERNAL_REG_BASE_ADDR);
  84. printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
  85. printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
  86. printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
  87. (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
  88. p_rx_buffer_base[0],
  89. (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
  90. printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
  91. (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
  92. p_tx_buffer_base[0],
  93. (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
  94. }
  95. #endif
  96. #define my_cpu_to_le32(x) my_le32_to_cpu((x))
  97. unsigned long my_le32_to_cpu (unsigned long x)
  98. {
  99. return (((x & 0x000000ffU) << 24) |
  100. ((x & 0x0000ff00U) << 8) |
  101. ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
  102. }
  103. /**********************************************************************
  104. * mv64360_eth_print_phy_status
  105. *
  106. * Prints gigabit ethenret phy status
  107. *
  108. * Input : pointer to ethernet interface network device structure
  109. * Output : N/A
  110. **********************************************************************/
  111. static void mv64360_eth_print_phy_status (struct eth_device *dev)
  112. {
  113. struct mv64360_eth_priv *port_private;
  114. unsigned int port_num;
  115. ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
  116. unsigned int port_status, phy_reg_data;
  117. port_private =
  118. (struct mv64360_eth_priv *) ethernet_private->port_private;
  119. port_num = port_private->port_num;
  120. /* Check Link status on phy */
  121. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  122. if (!(phy_reg_data & 0x20)) {
  123. printf ("Ethernet port changed link status to DOWN\n");
  124. } else {
  125. port_status =
  126. MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
  127. printf ("Ethernet status port %d: Link up", port_num);
  128. printf (", %s",
  129. (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
  130. if (port_status & BIT4)
  131. printf (", Speed 1 Gbps");
  132. else
  133. printf (", %s",
  134. (port_status & BIT5) ? "Speed 100 Mbps" :
  135. "Speed 10 Mbps");
  136. printf ("\n");
  137. }
  138. }
  139. /**********************************************************************
  140. * u-boot entry functions for mv64360_eth
  141. *
  142. **********************************************************************/
  143. int db64360_eth_probe (struct eth_device *dev)
  144. {
  145. return ((int) db64360_eth_start (dev));
  146. }
  147. int db64360_eth_poll (struct eth_device *dev)
  148. {
  149. return mv64360_eth_receive (dev);
  150. }
  151. int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
  152. {
  153. mv64360_eth_xmit (dev, packet, length);
  154. return 0;
  155. }
  156. void db64360_eth_disable (struct eth_device *dev)
  157. {
  158. mv64360_eth_stop (dev);
  159. }
  160. void mv6436x_eth_initialize (bd_t * bis)
  161. {
  162. struct eth_device *dev;
  163. ETH_PORT_INFO *ethernet_private;
  164. struct mv64360_eth_priv *port_private;
  165. int devnum, x, temp;
  166. char *s, *e, buf[64];
  167. for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
  168. dev = calloc (sizeof (*dev), 1);
  169. if (!dev) {
  170. printf ("%s: mv_enet%d allocation failure, %s\n",
  171. __FUNCTION__, devnum, "eth_device structure");
  172. return;
  173. }
  174. /* must be less than sizeof(dev->name) */
  175. sprintf (dev->name, "mv_enet%d", devnum);
  176. #ifdef DEBUG
  177. printf ("Initializing %s\n", dev->name);
  178. #endif
  179. /* Extract the MAC address from the environment */
  180. switch (devnum) {
  181. case 0:
  182. s = "ethaddr";
  183. break;
  184. case 1:
  185. s = "eth1addr";
  186. break;
  187. case 2:
  188. s = "eth2addr";
  189. break;
  190. default: /* this should never happen */
  191. printf ("%s: Invalid device number %d\n",
  192. __FUNCTION__, devnum);
  193. return;
  194. }
  195. temp = getenv_f(s, buf, sizeof (buf));
  196. s = (temp > 0) ? buf : NULL;
  197. #ifdef DEBUG
  198. printf ("Setting MAC %d to %s\n", devnum, s);
  199. #endif
  200. for (x = 0; x < 6; ++x) {
  201. dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
  202. if (s)
  203. s = (*e) ? e + 1 : e;
  204. }
  205. /* ronen - set the MAC addr in the HW */
  206. eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
  207. dev->init = (void *) db64360_eth_probe;
  208. dev->halt = (void *) ethernet_phy_reset;
  209. dev->send = (void *) db64360_eth_transmit;
  210. dev->recv = (void *) db64360_eth_poll;
  211. ethernet_private =
  212. calloc (sizeof (*ethernet_private), 1);
  213. dev->priv = (void *) ethernet_private;
  214. if (!ethernet_private) {
  215. printf ("%s: %s allocation failure, %s\n",
  216. __FUNCTION__, dev->name,
  217. "Private Device Structure");
  218. free (dev);
  219. return;
  220. }
  221. /* start with an zeroed ETH_PORT_INFO */
  222. memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
  223. memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
  224. /* set pointer to memory for stats data structure etc... */
  225. port_private =
  226. calloc (sizeof (*ethernet_private), 1);
  227. ethernet_private->port_private = (void *)port_private;
  228. if (!port_private) {
  229. printf ("%s: %s allocation failure, %s\n",
  230. __FUNCTION__, dev->name,
  231. "Port Private Device Structure");
  232. free (ethernet_private);
  233. free (dev);
  234. return;
  235. }
  236. port_private->stats =
  237. calloc (sizeof (struct net_device_stats), 1);
  238. if (!port_private->stats) {
  239. printf ("%s: %s allocation failure, %s\n",
  240. __FUNCTION__, dev->name,
  241. "Net stat Structure");
  242. free (port_private);
  243. free (ethernet_private);
  244. free (dev);
  245. return;
  246. }
  247. memset (ethernet_private->port_private, 0,
  248. sizeof (struct mv64360_eth_priv));
  249. switch (devnum) {
  250. case 0:
  251. ethernet_private->port_num = ETH_0;
  252. break;
  253. case 1:
  254. ethernet_private->port_num = ETH_1;
  255. break;
  256. case 2:
  257. ethernet_private->port_num = ETH_2;
  258. break;
  259. default:
  260. printf ("Invalid device number %d\n", devnum);
  261. break;
  262. };
  263. port_private->port_num = devnum;
  264. /*
  265. * Read MIB counter on the GT in order to reset them,
  266. * then zero all the stats fields in memory
  267. */
  268. mv64360_eth_update_stat (dev);
  269. memset (port_private->stats, 0,
  270. sizeof (struct net_device_stats));
  271. /* Extract the MAC address from the environment */
  272. switch (devnum) {
  273. case 0:
  274. s = "ethaddr";
  275. break;
  276. case 1:
  277. s = "eth1addr";
  278. break;
  279. case 2:
  280. s = "eth2addr";
  281. break;
  282. default: /* this should never happen */
  283. printf ("%s: Invalid device number %d\n",
  284. __FUNCTION__, devnum);
  285. return;
  286. }
  287. temp = getenv_f(s, buf, sizeof (buf));
  288. s = (temp > 0) ? buf : NULL;
  289. #ifdef DEBUG
  290. printf ("Setting MAC %d to %s\n", devnum, s);
  291. #endif
  292. for (x = 0; x < 6; ++x) {
  293. dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
  294. if (s)
  295. s = (*e) ? e + 1 : e;
  296. }
  297. DP (printf ("Allocating descriptor and buffer rings\n"));
  298. ethernet_private->p_rx_desc_area_base[0] =
  299. (ETH_RX_DESC *) memalign (16,
  300. RX_DESC_ALIGNED_SIZE *
  301. MV64360_RX_QUEUE_SIZE + 1);
  302. ethernet_private->p_tx_desc_area_base[0] =
  303. (ETH_TX_DESC *) memalign (16,
  304. TX_DESC_ALIGNED_SIZE *
  305. MV64360_TX_QUEUE_SIZE + 1);
  306. ethernet_private->p_rx_buffer_base[0] =
  307. (char *) memalign (16,
  308. MV64360_RX_QUEUE_SIZE *
  309. MV64360_TX_BUFFER_SIZE + 1);
  310. ethernet_private->p_tx_buffer_base[0] =
  311. (char *) memalign (16,
  312. MV64360_RX_QUEUE_SIZE *
  313. MV64360_TX_BUFFER_SIZE + 1);
  314. #ifdef DEBUG_MV_ETH
  315. /* DEBUG OUTPUT prints adresses of globals */
  316. print_globals (dev);
  317. #endif
  318. eth_register (dev);
  319. }
  320. DP (printf ("%s: exit\n", __FUNCTION__));
  321. }
  322. /**********************************************************************
  323. * mv64360_eth_open
  324. *
  325. * This function is called when openning the network device. The function
  326. * should initialize all the hardware, initialize cyclic Rx/Tx
  327. * descriptors chain and buffers and allocate an IRQ to the network
  328. * device.
  329. *
  330. * Input : a pointer to the network device structure
  331. * / / ronen - changed the output to match net/eth.c needs
  332. * Output : nonzero of success , zero if fails.
  333. * under construction
  334. **********************************************************************/
  335. int mv64360_eth_open (struct eth_device *dev)
  336. {
  337. return (mv64360_eth_real_open (dev));
  338. }
  339. /* Helper function for mv64360_eth_open */
  340. static int mv64360_eth_real_open (struct eth_device *dev)
  341. {
  342. unsigned int queue;
  343. ETH_PORT_INFO *ethernet_private;
  344. struct mv64360_eth_priv *port_private;
  345. unsigned int port_num;
  346. u32 phy_reg_data;
  347. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  348. /* ronen - when we update the MAC env params we only update dev->enetaddr
  349. see ./net/eth.c eth_set_enetaddr() */
  350. memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
  351. port_private =
  352. (struct mv64360_eth_priv *) ethernet_private->port_private;
  353. port_num = port_private->port_num;
  354. /* Stop RX Queues */
  355. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
  356. 0x0000ff00);
  357. /* Clear the ethernet port interrupts */
  358. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
  359. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
  360. /* Unmask RX buffer and TX end interrupt */
  361. MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
  362. INT_CAUSE_UNMASK_ALL);
  363. /* Unmask phy and link status changes interrupts */
  364. MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
  365. INT_CAUSE_UNMASK_ALL_EXT);
  366. /* Set phy address of the port */
  367. ethernet_private->port_phy_addr = 0x8 + port_num;
  368. /* Activate the DMA channels etc */
  369. eth_port_init (ethernet_private);
  370. /* "Allocate" setup TX rings */
  371. for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
  372. unsigned int size;
  373. port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
  374. size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
  375. ethernet_private->tx_desc_area_size[queue] = size;
  376. /* first clear desc area completely */
  377. memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
  378. 0, ethernet_private->tx_desc_area_size[queue]);
  379. /* initialize tx desc ring with low level driver */
  380. if (ether_init_tx_desc_ring
  381. (ethernet_private, ETH_Q0,
  382. port_private->tx_ring_size[queue],
  383. MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
  384. (unsigned int) ethernet_private->
  385. p_tx_desc_area_base[queue],
  386. (unsigned int) ethernet_private->
  387. p_tx_buffer_base[queue]) == false)
  388. printf ("### Error initializing TX Ring\n");
  389. }
  390. /* "Allocate" setup RX rings */
  391. for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
  392. unsigned int size;
  393. /* Meantime RX Ring are fixed - but must be configurable by user */
  394. port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
  395. size = (port_private->rx_ring_size[queue] *
  396. RX_DESC_ALIGNED_SIZE);
  397. ethernet_private->rx_desc_area_size[queue] = size;
  398. /* first clear desc area completely */
  399. memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
  400. 0, ethernet_private->rx_desc_area_size[queue]);
  401. if ((ether_init_rx_desc_ring
  402. (ethernet_private, ETH_Q0,
  403. port_private->rx_ring_size[queue],
  404. MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
  405. (unsigned int) ethernet_private->
  406. p_rx_desc_area_base[queue],
  407. (unsigned int) ethernet_private->
  408. p_rx_buffer_base[queue])) == false)
  409. printf ("### Error initializing RX Ring\n");
  410. }
  411. eth_port_start (ethernet_private);
  412. /* Set maximum receive buffer to 9700 bytes */
  413. MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
  414. (0x5 << 17) |
  415. (MV_REG_READ
  416. (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
  417. & 0xfff1ffff));
  418. /*
  419. * Set ethernet MTU for leaky bucket mechanism to 0 - this will
  420. * disable the leaky bucket mechanism .
  421. */
  422. MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
  423. MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
  424. /* Check Link status on phy */
  425. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  426. if (!(phy_reg_data & 0x20)) {
  427. /* Reset PHY */
  428. if ((ethernet_phy_reset (port_num)) != true) {
  429. printf ("$$ Warnning: No link on port %d \n",
  430. port_num);
  431. return 0;
  432. } else {
  433. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  434. if (!(phy_reg_data & 0x20)) {
  435. printf ("### Error: Phy is not active\n");
  436. return 0;
  437. }
  438. }
  439. } else {
  440. mv64360_eth_print_phy_status (dev);
  441. }
  442. port_private->eth_running = MAGIC_ETH_RUNNING;
  443. return 1;
  444. }
  445. static int mv64360_eth_free_tx_rings (struct eth_device *dev)
  446. {
  447. unsigned int queue;
  448. ETH_PORT_INFO *ethernet_private;
  449. struct mv64360_eth_priv *port_private;
  450. unsigned int port_num;
  451. volatile ETH_TX_DESC *p_tx_curr_desc;
  452. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  453. port_private =
  454. (struct mv64360_eth_priv *) ethernet_private->port_private;
  455. port_num = port_private->port_num;
  456. /* Stop Tx Queues */
  457. MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
  458. 0x0000ff00);
  459. /* Free TX rings */
  460. DP (printf ("Clearing previously allocated TX queues... "));
  461. for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
  462. /* Free on TX rings */
  463. for (p_tx_curr_desc =
  464. ethernet_private->p_tx_desc_area_base[queue];
  465. ((unsigned int) p_tx_curr_desc <= (unsigned int)
  466. ethernet_private->p_tx_desc_area_base[queue] +
  467. ethernet_private->tx_desc_area_size[queue]);
  468. p_tx_curr_desc =
  469. (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
  470. TX_DESC_ALIGNED_SIZE)) {
  471. /* this is inside for loop */
  472. if (p_tx_curr_desc->return_info != 0) {
  473. p_tx_curr_desc->return_info = 0;
  474. DP (printf ("freed\n"));
  475. }
  476. }
  477. DP (printf ("Done\n"));
  478. }
  479. return 0;
  480. }
  481. static int mv64360_eth_free_rx_rings (struct eth_device *dev)
  482. {
  483. unsigned int queue;
  484. ETH_PORT_INFO *ethernet_private;
  485. struct mv64360_eth_priv *port_private;
  486. unsigned int port_num;
  487. volatile ETH_RX_DESC *p_rx_curr_desc;
  488. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  489. port_private =
  490. (struct mv64360_eth_priv *) ethernet_private->port_private;
  491. port_num = port_private->port_num;
  492. /* Stop RX Queues */
  493. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
  494. 0x0000ff00);
  495. /* Free RX rings */
  496. DP (printf ("Clearing previously allocated RX queues... "));
  497. for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
  498. /* Free preallocated skb's on RX rings */
  499. for (p_rx_curr_desc =
  500. ethernet_private->p_rx_desc_area_base[queue];
  501. (((unsigned int) p_rx_curr_desc <
  502. ((unsigned int) ethernet_private->
  503. p_rx_desc_area_base[queue] +
  504. ethernet_private->rx_desc_area_size[queue])));
  505. p_rx_curr_desc =
  506. (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
  507. RX_DESC_ALIGNED_SIZE)) {
  508. if (p_rx_curr_desc->return_info != 0) {
  509. p_rx_curr_desc->return_info = 0;
  510. DP (printf ("freed\n"));
  511. }
  512. }
  513. DP (printf ("Done\n"));
  514. }
  515. return 0;
  516. }
  517. /**********************************************************************
  518. * mv64360_eth_stop
  519. *
  520. * This function is used when closing the network device.
  521. * It updates the hardware,
  522. * release all memory that holds buffers and descriptors and release the IRQ.
  523. * Input : a pointer to the device structure
  524. * Output : zero if success , nonzero if fails
  525. *********************************************************************/
  526. int mv64360_eth_stop (struct eth_device *dev)
  527. {
  528. /* Disable all gigE address decoder */
  529. MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
  530. DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
  531. mv64360_eth_real_stop (dev);
  532. return 0;
  533. };
  534. /* Helper function for mv64360_eth_stop */
  535. static int mv64360_eth_real_stop (struct eth_device *dev)
  536. {
  537. ETH_PORT_INFO *ethernet_private;
  538. struct mv64360_eth_priv *port_private;
  539. unsigned int port_num;
  540. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  541. port_private =
  542. (struct mv64360_eth_priv *) ethernet_private->port_private;
  543. port_num = port_private->port_num;
  544. mv64360_eth_free_tx_rings (dev);
  545. mv64360_eth_free_rx_rings (dev);
  546. eth_port_reset (ethernet_private->port_num);
  547. /* Disable ethernet port interrupts */
  548. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
  549. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
  550. /* Mask RX buffer and TX end interrupt */
  551. MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
  552. /* Mask phy and link status changes interrupts */
  553. MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
  554. MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
  555. BIT0 << port_num);
  556. /* Print Network statistics */
  557. #ifndef UPDATE_STATS_BY_SOFTWARE
  558. /*
  559. * Print statistics (only if ethernet is running),
  560. * then zero all the stats fields in memory
  561. */
  562. if (port_private->eth_running == MAGIC_ETH_RUNNING) {
  563. port_private->eth_running = 0;
  564. mv64360_eth_print_stat (dev);
  565. }
  566. memset (port_private->stats, 0, sizeof (struct net_device_stats));
  567. #endif
  568. DP (printf ("\nEthernet stopped ... \n"));
  569. return 0;
  570. }
  571. /**********************************************************************
  572. * mv64360_eth_start_xmit
  573. *
  574. * This function is queues a packet in the Tx descriptor for
  575. * required port.
  576. *
  577. * Input : skb - a pointer to socket buffer
  578. * dev - a pointer to the required port
  579. *
  580. * Output : zero upon success
  581. **********************************************************************/
  582. int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
  583. int dataSize)
  584. {
  585. ETH_PORT_INFO *ethernet_private;
  586. struct mv64360_eth_priv *port_private;
  587. PKT_INFO pkt_info;
  588. ETH_FUNC_RET_STATUS status;
  589. struct net_device_stats *stats;
  590. ETH_FUNC_RET_STATUS release_result;
  591. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  592. port_private =
  593. (struct mv64360_eth_priv *) ethernet_private->port_private;
  594. stats = port_private->stats;
  595. /* Update packet info data structure */
  596. pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
  597. pkt_info.byte_cnt = dataSize;
  598. pkt_info.buf_ptr = (unsigned int) dataPtr;
  599. pkt_info.return_info = 0;
  600. status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
  601. if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
  602. printf ("Error on transmitting packet ..");
  603. if (status == ETH_QUEUE_FULL)
  604. printf ("ETH Queue is full. \n");
  605. if (status == ETH_QUEUE_LAST_RESOURCE)
  606. printf ("ETH Queue: using last available resource. \n");
  607. goto error;
  608. }
  609. /* Update statistics and start of transmittion time */
  610. stats->tx_bytes += dataSize;
  611. stats->tx_packets++;
  612. /* Check if packet(s) is(are) transmitted correctly (release everything) */
  613. do {
  614. release_result =
  615. eth_tx_return_desc (ethernet_private, ETH_Q0,
  616. &pkt_info);
  617. switch (release_result) {
  618. case ETH_OK:
  619. DP (printf ("descriptor released\n"));
  620. if (pkt_info.cmd_sts & BIT0) {
  621. printf ("Error in TX\n");
  622. stats->tx_errors++;
  623. }
  624. break;
  625. case ETH_RETRY:
  626. DP (printf ("transmission still in process\n"));
  627. break;
  628. case ETH_ERROR:
  629. printf ("routine can not access Tx desc ring\n");
  630. break;
  631. case ETH_END_OF_JOB:
  632. DP (printf ("the routine has nothing to release\n"));
  633. break;
  634. default: /* should not happen */
  635. break;
  636. }
  637. } while (release_result == ETH_OK);
  638. return 0; /* success */
  639. error:
  640. return 1; /* Failed - higher layers will free the skb */
  641. }
  642. /**********************************************************************
  643. * mv64360_eth_receive
  644. *
  645. * This function is forward packets that are received from the port's
  646. * queues toward kernel core or FastRoute them to another interface.
  647. *
  648. * Input : dev - a pointer to the required interface
  649. * max - maximum number to receive (0 means unlimted)
  650. *
  651. * Output : number of served packets
  652. **********************************************************************/
  653. int mv64360_eth_receive (struct eth_device *dev)
  654. {
  655. ETH_PORT_INFO *ethernet_private;
  656. struct mv64360_eth_priv *port_private;
  657. PKT_INFO pkt_info;
  658. struct net_device_stats *stats;
  659. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  660. port_private =
  661. (struct mv64360_eth_priv *) ethernet_private->port_private;
  662. stats = port_private->stats;
  663. while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
  664. ETH_OK)) {
  665. #ifdef DEBUG_MV_ETH
  666. if (pkt_info.byte_cnt != 0) {
  667. printf ("%s: Received %d byte Packet @ 0x%x\n",
  668. __FUNCTION__, pkt_info.byte_cnt,
  669. pkt_info.buf_ptr);
  670. }
  671. #endif
  672. /* Update statistics. Note byte count includes 4 byte CRC count */
  673. stats->rx_packets++;
  674. stats->rx_bytes += pkt_info.byte_cnt;
  675. /*
  676. * In case received a packet without first / last bits on OR the error
  677. * summary bit is on, the packets needs to be dropeed.
  678. */
  679. if (((pkt_info.
  680. cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
  681. (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
  682. || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
  683. stats->rx_dropped++;
  684. printf ("Received packet spread on multiple descriptors\n");
  685. /* Is this caused by an error ? */
  686. if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
  687. stats->rx_errors++;
  688. }
  689. /* free these descriptors again without forwarding them to the higher layers */
  690. pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
  691. pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
  692. if (eth_rx_return_buff
  693. (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
  694. printf ("Error while returning the RX Desc to Ring\n");
  695. } else {
  696. DP (printf ("RX Desc returned to Ring\n"));
  697. }
  698. /* /free these descriptors again */
  699. } else {
  700. /* !!! call higher layer processing */
  701. #ifdef DEBUG_MV_ETH
  702. printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
  703. #endif
  704. /* let the upper layer handle the packet */
  705. NetReceive ((uchar *) pkt_info.buf_ptr,
  706. (int) pkt_info.byte_cnt);
  707. /* **************************************************************** */
  708. /* free descriptor */
  709. pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
  710. pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
  711. DP (printf
  712. ("RX: pkt_info.buf_ptr = %x\n",
  713. pkt_info.buf_ptr));
  714. if (eth_rx_return_buff
  715. (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
  716. printf ("Error while returning the RX Desc to Ring\n");
  717. } else {
  718. DP (printf ("RX Desc returned to Ring\n"));
  719. }
  720. /* **************************************************************** */
  721. }
  722. }
  723. mv64360_eth_get_stats (dev); /* update statistics */
  724. return 1;
  725. }
  726. /**********************************************************************
  727. * mv64360_eth_get_stats
  728. *
  729. * Returns a pointer to the interface statistics.
  730. *
  731. * Input : dev - a pointer to the required interface
  732. *
  733. * Output : a pointer to the interface's statistics
  734. **********************************************************************/
  735. static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
  736. {
  737. ETH_PORT_INFO *ethernet_private;
  738. struct mv64360_eth_priv *port_private;
  739. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  740. port_private =
  741. (struct mv64360_eth_priv *) ethernet_private->port_private;
  742. mv64360_eth_update_stat (dev);
  743. return port_private->stats;
  744. }
  745. /**********************************************************************
  746. * mv64360_eth_update_stat
  747. *
  748. * Update the statistics structure in the private data structure
  749. *
  750. * Input : pointer to ethernet interface network device structure
  751. * Output : N/A
  752. **********************************************************************/
  753. static void mv64360_eth_update_stat (struct eth_device *dev)
  754. {
  755. ETH_PORT_INFO *ethernet_private;
  756. struct mv64360_eth_priv *port_private;
  757. struct net_device_stats *stats;
  758. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  759. port_private =
  760. (struct mv64360_eth_priv *) ethernet_private->port_private;
  761. stats = port_private->stats;
  762. /* These are false updates */
  763. stats->rx_packets += (unsigned long)
  764. eth_read_mib_counter (ethernet_private->port_num,
  765. ETH_MIB_GOOD_FRAMES_RECEIVED);
  766. stats->tx_packets += (unsigned long)
  767. eth_read_mib_counter (ethernet_private->port_num,
  768. ETH_MIB_GOOD_FRAMES_SENT);
  769. stats->rx_bytes += (unsigned long)
  770. eth_read_mib_counter (ethernet_private->port_num,
  771. ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
  772. /*
  773. * Ideally this should be as follows -
  774. *
  775. * stats->rx_bytes += stats->rx_bytes +
  776. * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
  777. * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
  778. *
  779. * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
  780. * is just a dummy read for proper work of the GigE port
  781. */
  782. (void)eth_read_mib_counter (ethernet_private->port_num,
  783. ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
  784. stats->tx_bytes += (unsigned long)
  785. eth_read_mib_counter (ethernet_private->port_num,
  786. ETH_MIB_GOOD_OCTETS_SENT_LOW);
  787. (void)eth_read_mib_counter (ethernet_private->port_num,
  788. ETH_MIB_GOOD_OCTETS_SENT_HIGH);
  789. stats->rx_errors += (unsigned long)
  790. eth_read_mib_counter (ethernet_private->port_num,
  791. ETH_MIB_MAC_RECEIVE_ERROR);
  792. /* Rx dropped is for received packet with CRC error */
  793. stats->rx_dropped +=
  794. (unsigned long) eth_read_mib_counter (ethernet_private->
  795. port_num,
  796. ETH_MIB_BAD_CRC_EVENT);
  797. stats->multicast += (unsigned long)
  798. eth_read_mib_counter (ethernet_private->port_num,
  799. ETH_MIB_MULTICAST_FRAMES_RECEIVED);
  800. stats->collisions +=
  801. (unsigned long) eth_read_mib_counter (ethernet_private->
  802. port_num,
  803. ETH_MIB_COLLISION) +
  804. (unsigned long) eth_read_mib_counter (ethernet_private->
  805. port_num,
  806. ETH_MIB_LATE_COLLISION);
  807. /* detailed rx errors */
  808. stats->rx_length_errors +=
  809. (unsigned long) eth_read_mib_counter (ethernet_private->
  810. port_num,
  811. ETH_MIB_UNDERSIZE_RECEIVED)
  812. +
  813. (unsigned long) eth_read_mib_counter (ethernet_private->
  814. port_num,
  815. ETH_MIB_OVERSIZE_RECEIVED);
  816. /* detailed tx errors */
  817. }
  818. #ifndef UPDATE_STATS_BY_SOFTWARE
  819. /**********************************************************************
  820. * mv64360_eth_print_stat
  821. *
  822. * Update the statistics structure in the private data structure
  823. *
  824. * Input : pointer to ethernet interface network device structure
  825. * Output : N/A
  826. **********************************************************************/
  827. static void mv64360_eth_print_stat (struct eth_device *dev)
  828. {
  829. ETH_PORT_INFO *ethernet_private;
  830. struct mv64360_eth_priv *port_private;
  831. struct net_device_stats *stats;
  832. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  833. port_private =
  834. (struct mv64360_eth_priv *) ethernet_private->port_private;
  835. stats = port_private->stats;
  836. /* These are false updates */
  837. printf ("\n### Network statistics: ###\n");
  838. printf ("--------------------------\n");
  839. printf (" Packets received: %ld\n", stats->rx_packets);
  840. printf (" Packets send: %ld\n", stats->tx_packets);
  841. printf (" Received bytes: %ld\n", stats->rx_bytes);
  842. printf (" Send bytes: %ld\n", stats->tx_bytes);
  843. if (stats->rx_errors != 0)
  844. printf (" Rx Errors: %ld\n",
  845. stats->rx_errors);
  846. if (stats->rx_dropped != 0)
  847. printf (" Rx dropped (CRC Errors): %ld\n",
  848. stats->rx_dropped);
  849. if (stats->multicast != 0)
  850. printf (" Rx mulicast frames: %ld\n",
  851. stats->multicast);
  852. if (stats->collisions != 0)
  853. printf (" No. of collisions: %ld\n",
  854. stats->collisions);
  855. if (stats->rx_length_errors != 0)
  856. printf (" Rx length errors: %ld\n",
  857. stats->rx_length_errors);
  858. }
  859. #endif
  860. /**************************************************************************
  861. *network_start - Network Kick Off Routine UBoot
  862. *Inputs :
  863. *Outputs :
  864. **************************************************************************/
  865. bool db64360_eth_start (struct eth_device *dev)
  866. {
  867. return (mv64360_eth_open (dev)); /* calls real open */
  868. }
  869. /*************************************************************************
  870. **************************************************************************
  871. **************************************************************************
  872. * The second part is the low level driver of the gigE ethernet ports. *
  873. **************************************************************************
  874. **************************************************************************
  875. *************************************************************************/
  876. /*
  877. * based on Linux code
  878. * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
  879. * Copyright (C) 2002 rabeeh@galileo.co.il
  880. */
  881. /********************************************************************************
  882. * Marvell's Gigabit Ethernet controller low level driver
  883. *
  884. * DESCRIPTION:
  885. * This file introduce low level API to Marvell's Gigabit Ethernet
  886. * controller. This Gigabit Ethernet Controller driver API controls
  887. * 1) Operations (i.e. port init, start, reset etc').
  888. * 2) Data flow (i.e. port send, receive etc').
  889. * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
  890. * struct.
  891. * This struct includes user configuration information as well as
  892. * driver internal data needed for its operations.
  893. *
  894. * Supported Features:
  895. * - This low level driver is OS independent. Allocating memory for
  896. * the descriptor rings and buffers are not within the scope of
  897. * this driver.
  898. * - The user is free from Rx/Tx queue managing.
  899. * - This low level driver introduce functionality API that enable
  900. * the to operate Marvell's Gigabit Ethernet Controller in a
  901. * convenient way.
  902. * - Simple Gigabit Ethernet port operation API.
  903. * - Simple Gigabit Ethernet port data flow API.
  904. * - Data flow and operation API support per queue functionality.
  905. * - Support cached descriptors for better performance.
  906. * - Enable access to all four DRAM banks and internal SRAM memory
  907. * spaces.
  908. * - PHY access and control API.
  909. * - Port control register configuration API.
  910. * - Full control over Unicast and Multicast MAC configurations.
  911. *
  912. * Operation flow:
  913. *
  914. * Initialization phase
  915. * This phase complete the initialization of the ETH_PORT_INFO
  916. * struct.
  917. * User information regarding port configuration has to be set
  918. * prior to calling the port initialization routine. For example,
  919. * the user has to assign the port_phy_addr field which is board
  920. * depended parameter.
  921. * In this phase any port Tx/Rx activity is halted, MIB counters
  922. * are cleared, PHY address is set according to user parameter and
  923. * access to DRAM and internal SRAM memory spaces.
  924. *
  925. * Driver ring initialization
  926. * Allocating memory for the descriptor rings and buffers is not
  927. * within the scope of this driver. Thus, the user is required to
  928. * allocate memory for the descriptors ring and buffers. Those
  929. * memory parameters are used by the Rx and Tx ring initialization
  930. * routines in order to curve the descriptor linked list in a form
  931. * of a ring.
  932. * Note: Pay special attention to alignment issues when using
  933. * cached descriptors/buffers. In this phase the driver store
  934. * information in the ETH_PORT_INFO struct regarding each queue
  935. * ring.
  936. *
  937. * Driver start
  938. * This phase prepares the Ethernet port for Rx and Tx activity.
  939. * It uses the information stored in the ETH_PORT_INFO struct to
  940. * initialize the various port registers.
  941. *
  942. * Data flow:
  943. * All packet references to/from the driver are done using PKT_INFO
  944. * struct.
  945. * This struct is a unified struct used with Rx and Tx operations.
  946. * This way the user is not required to be familiar with neither
  947. * Tx nor Rx descriptors structures.
  948. * The driver's descriptors rings are management by indexes.
  949. * Those indexes controls the ring resources and used to indicate
  950. * a SW resource error:
  951. * 'current'
  952. * This index points to the current available resource for use. For
  953. * example in Rx process this index will point to the descriptor
  954. * that will be passed to the user upon calling the receive routine.
  955. * In Tx process, this index will point to the descriptor
  956. * that will be assigned with the user packet info and transmitted.
  957. * 'used'
  958. * This index points to the descriptor that need to restore its
  959. * resources. For example in Rx process, using the Rx buffer return
  960. * API will attach the buffer returned in packet info to the
  961. * descriptor pointed by 'used'. In Tx process, using the Tx
  962. * descriptor return will merely return the user packet info with
  963. * the command status of the transmitted buffer pointed by the
  964. * 'used' index. Nevertheless, it is essential to use this routine
  965. * to update the 'used' index.
  966. * 'first'
  967. * This index supports Tx Scatter-Gather. It points to the first
  968. * descriptor of a packet assembled of multiple buffers. For example
  969. * when in middle of Such packet we have a Tx resource error the
  970. * 'curr' index get the value of 'first' to indicate that the ring
  971. * returned to its state before trying to transmit this packet.
  972. *
  973. * Receive operation:
  974. * The eth_port_receive API set the packet information struct,
  975. * passed by the caller, with received information from the
  976. * 'current' SDMA descriptor.
  977. * It is the user responsibility to return this resource back
  978. * to the Rx descriptor ring to enable the reuse of this source.
  979. * Return Rx resource is done using the eth_rx_return_buff API.
  980. *
  981. * Transmit operation:
  982. * The eth_port_send API supports Scatter-Gather which enables to
  983. * send a packet spanned over multiple buffers. This means that
  984. * for each packet info structure given by the user and put into
  985. * the Tx descriptors ring, will be transmitted only if the 'LAST'
  986. * bit will be set in the packet info command status field. This
  987. * API also consider restriction regarding buffer alignments and
  988. * sizes.
  989. * The user must return a Tx resource after ensuring the buffer
  990. * has been transmitted to enable the Tx ring indexes to update.
  991. *
  992. * BOARD LAYOUT
  993. * This device is on-board. No jumper diagram is necessary.
  994. *
  995. * EXTERNAL INTERFACE
  996. *
  997. * Prior to calling the initialization routine eth_port_init() the user
  998. * must set the following fields under ETH_PORT_INFO struct:
  999. * port_num User Ethernet port number.
  1000. * port_phy_addr User PHY address of Ethernet port.
  1001. * port_mac_addr[6] User defined port MAC address.
  1002. * port_config User port configuration value.
  1003. * port_config_extend User port config extend value.
  1004. * port_sdma_config User port SDMA config value.
  1005. * port_serial_control User port serial control value.
  1006. * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
  1007. * *port_private User scratch pad for user specific data structures.
  1008. *
  1009. * This driver introduce a set of default values:
  1010. * PORT_CONFIG_VALUE Default port configuration value
  1011. * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
  1012. * PORT_SDMA_CONFIG_VALUE Default sdma control value
  1013. * PORT_SERIAL_CONTROL_VALUE Default port serial control value
  1014. *
  1015. * This driver data flow is done using the PKT_INFO struct which is
  1016. * a unified struct for Rx and Tx operations:
  1017. * byte_cnt Tx/Rx descriptor buffer byte count.
  1018. * l4i_chk CPU provided TCP Checksum. For Tx operation only.
  1019. * cmd_sts Tx/Rx descriptor command status.
  1020. * buf_ptr Tx/Rx descriptor buffer pointer.
  1021. * return_info Tx/Rx user resource return information.
  1022. *
  1023. *
  1024. * EXTERNAL SUPPORT REQUIREMENTS
  1025. *
  1026. * This driver requires the following external support:
  1027. *
  1028. * D_CACHE_FLUSH_LINE (address, address offset)
  1029. *
  1030. * This macro applies assembly code to flush and invalidate cache
  1031. * line.
  1032. * address - address base.
  1033. * address offset - address offset
  1034. *
  1035. *
  1036. * CPU_PIPE_FLUSH
  1037. *
  1038. * This macro applies assembly code to flush the CPU pipeline.
  1039. *
  1040. *******************************************************************************/
  1041. /* includes */
  1042. /* defines */
  1043. /* SDMA command macros */
  1044. #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
  1045. MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
  1046. #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
  1047. MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
  1048. (1 << (8 + tx_queue)))
  1049. #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
  1050. MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
  1051. #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
  1052. MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
  1053. #define CURR_RFD_GET(p_curr_desc, queue) \
  1054. ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
  1055. #define CURR_RFD_SET(p_curr_desc, queue) \
  1056. (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
  1057. #define USED_RFD_GET(p_used_desc, queue) \
  1058. ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
  1059. #define USED_RFD_SET(p_used_desc, queue)\
  1060. (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
  1061. #define CURR_TFD_GET(p_curr_desc, queue) \
  1062. ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
  1063. #define CURR_TFD_SET(p_curr_desc, queue) \
  1064. (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
  1065. #define USED_TFD_GET(p_used_desc, queue) \
  1066. ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
  1067. #define USED_TFD_SET(p_used_desc, queue) \
  1068. (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
  1069. #define FIRST_TFD_GET(p_first_desc, queue) \
  1070. ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
  1071. #define FIRST_TFD_SET(p_first_desc, queue) \
  1072. (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
  1073. /* Macros that save access to desc in order to find next desc pointer */
  1074. #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
  1075. #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
  1076. #define LINK_UP_TIMEOUT 100000
  1077. #define PHY_BUSY_TIMEOUT 10000000
  1078. /* locals */
  1079. /* PHY routines */
  1080. static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
  1081. static int ethernet_phy_get (ETH_PORT eth_port_num);
  1082. /* Ethernet Port routines */
  1083. static void eth_set_access_control (ETH_PORT eth_port_num,
  1084. ETH_WIN_PARAM * param);
  1085. static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
  1086. ETH_QUEUE queue, int option);
  1087. #if 0 /* FIXME */
  1088. static bool eth_port_smc_addr (ETH_PORT eth_port_num,
  1089. unsigned char mc_byte,
  1090. ETH_QUEUE queue, int option);
  1091. static bool eth_port_omc_addr (ETH_PORT eth_port_num,
  1092. unsigned char crc8,
  1093. ETH_QUEUE queue, int option);
  1094. #endif
  1095. static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
  1096. int byte_count);
  1097. void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
  1098. typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
  1099. u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
  1100. {
  1101. u32 result = 0;
  1102. u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
  1103. if (enable & (1 << bank))
  1104. return 0;
  1105. if (bank == BANK0)
  1106. result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
  1107. if (bank == BANK1)
  1108. result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
  1109. if (bank == BANK2)
  1110. result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
  1111. if (bank == BANK3)
  1112. result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
  1113. result &= 0x0000ffff;
  1114. result = result << 16;
  1115. return result;
  1116. }
  1117. u32 mv_get_dram_bank_size (MEMORY_BANK bank)
  1118. {
  1119. u32 result = 0;
  1120. u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
  1121. if (enable & (1 << bank))
  1122. return 0;
  1123. if (bank == BANK0)
  1124. result = MV_REG_READ (MV64360_CS_0_SIZE);
  1125. if (bank == BANK1)
  1126. result = MV_REG_READ (MV64360_CS_1_SIZE);
  1127. if (bank == BANK2)
  1128. result = MV_REG_READ (MV64360_CS_2_SIZE);
  1129. if (bank == BANK3)
  1130. result = MV_REG_READ (MV64360_CS_3_SIZE);
  1131. result += 1;
  1132. result &= 0x0000ffff;
  1133. result = result << 16;
  1134. return result;
  1135. }
  1136. u32 mv_get_internal_sram_base (void)
  1137. {
  1138. u32 result;
  1139. result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
  1140. result &= 0x0000ffff;
  1141. result = result << 16;
  1142. return result;
  1143. }
  1144. /*******************************************************************************
  1145. * eth_port_init - Initialize the Ethernet port driver
  1146. *
  1147. * DESCRIPTION:
  1148. * This function prepares the ethernet port to start its activity:
  1149. * 1) Completes the ethernet port driver struct initialization toward port
  1150. * start routine.
  1151. * 2) Resets the device to a quiescent state in case of warm reboot.
  1152. * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
  1153. * 4) Clean MAC tables. The reset status of those tables is unknown.
  1154. * 5) Set PHY address.
  1155. * Note: Call this routine prior to eth_port_start routine and after setting
  1156. * user values in the user fields of Ethernet port control struct (i.e.
  1157. * port_phy_addr).
  1158. *
  1159. * INPUT:
  1160. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
  1161. *
  1162. * OUTPUT:
  1163. * See description.
  1164. *
  1165. * RETURN:
  1166. * None.
  1167. *
  1168. *******************************************************************************/
  1169. static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
  1170. {
  1171. int queue;
  1172. ETH_WIN_PARAM win_param;
  1173. p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
  1174. p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
  1175. p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
  1176. p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
  1177. p_eth_port_ctrl->port_rx_queue_command = 0;
  1178. p_eth_port_ctrl->port_tx_queue_command = 0;
  1179. /* Zero out SW structs */
  1180. for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
  1181. CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
  1182. USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
  1183. p_eth_port_ctrl->rx_resource_err[queue] = false;
  1184. }
  1185. for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
  1186. CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1187. USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1188. FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1189. p_eth_port_ctrl->tx_resource_err[queue] = false;
  1190. }
  1191. eth_port_reset (p_eth_port_ctrl->port_num);
  1192. /* Set access parameters for DRAM bank 0 */
  1193. win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
  1194. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1195. win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
  1196. #ifndef CONFIG_NOT_COHERENT_CACHE
  1197. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1198. #endif
  1199. win_param.high_addr = 0;
  1200. /* Get bank base */
  1201. win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
  1202. win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
  1203. if (win_param.size == 0)
  1204. win_param.enable = 0;
  1205. else
  1206. win_param.enable = 1; /* Enable the access */
  1207. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1208. /* Set the access control for address window (EPAPR) READ & WRITE */
  1209. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1210. /* Set access parameters for DRAM bank 1 */
  1211. win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
  1212. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1213. win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
  1214. #ifndef CONFIG_NOT_COHERENT_CACHE
  1215. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1216. #endif
  1217. win_param.high_addr = 0;
  1218. /* Get bank base */
  1219. win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
  1220. win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
  1221. if (win_param.size == 0)
  1222. win_param.enable = 0;
  1223. else
  1224. win_param.enable = 1; /* Enable the access */
  1225. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1226. /* Set the access control for address window (EPAPR) READ & WRITE */
  1227. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1228. /* Set access parameters for DRAM bank 2 */
  1229. win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
  1230. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1231. win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
  1232. #ifndef CONFIG_NOT_COHERENT_CACHE
  1233. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1234. #endif
  1235. win_param.high_addr = 0;
  1236. /* Get bank base */
  1237. win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
  1238. win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
  1239. if (win_param.size == 0)
  1240. win_param.enable = 0;
  1241. else
  1242. win_param.enable = 1; /* Enable the access */
  1243. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1244. /* Set the access control for address window (EPAPR) READ & WRITE */
  1245. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1246. /* Set access parameters for DRAM bank 3 */
  1247. win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
  1248. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1249. win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
  1250. #ifndef CONFIG_NOT_COHERENT_CACHE
  1251. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1252. #endif
  1253. win_param.high_addr = 0;
  1254. /* Get bank base */
  1255. win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
  1256. win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
  1257. if (win_param.size == 0)
  1258. win_param.enable = 0;
  1259. else
  1260. win_param.enable = 1; /* Enable the access */
  1261. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1262. /* Set the access control for address window (EPAPR) READ & WRITE */
  1263. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1264. /* Set access parameters for Internal SRAM */
  1265. win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
  1266. win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
  1267. win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
  1268. win_param.high_addr = 0;
  1269. win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
  1270. win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
  1271. win_param.enable = 1; /* Enable the access */
  1272. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1273. /* Set the access control for address window (EPAPR) READ & WRITE */
  1274. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1275. eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
  1276. ethernet_phy_set (p_eth_port_ctrl->port_num,
  1277. p_eth_port_ctrl->port_phy_addr);
  1278. return;
  1279. }
  1280. /*******************************************************************************
  1281. * eth_port_start - Start the Ethernet port activity.
  1282. *
  1283. * DESCRIPTION:
  1284. * This routine prepares the Ethernet port for Rx and Tx activity:
  1285. * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
  1286. * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
  1287. * for Tx and ether_init_rx_desc_ring for Rx)
  1288. * 2. Initialize and enable the Ethernet configuration port by writing to
  1289. * the port's configuration and command registers.
  1290. * 3. Initialize and enable the SDMA by writing to the SDMA's
  1291. * configuration and command registers.
  1292. * After completing these steps, the ethernet port SDMA can starts to
  1293. * perform Rx and Tx activities.
  1294. *
  1295. * Note: Each Rx and Tx queue descriptor's list must be initialized prior
  1296. * to calling this function (use ether_init_tx_desc_ring for Tx queues and
  1297. * ether_init_rx_desc_ring for Rx queues).
  1298. *
  1299. * INPUT:
  1300. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
  1301. *
  1302. * OUTPUT:
  1303. * Ethernet port is ready to receive and transmit.
  1304. *
  1305. * RETURN:
  1306. * false if the port PHY is not up.
  1307. * true otherwise.
  1308. *
  1309. *******************************************************************************/
  1310. static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
  1311. {
  1312. int queue;
  1313. volatile ETH_TX_DESC *p_tx_curr_desc;
  1314. volatile ETH_RX_DESC *p_rx_curr_desc;
  1315. unsigned int phy_reg_data;
  1316. ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
  1317. /* Assignment of Tx CTRP of given queue */
  1318. for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
  1319. CURR_TFD_GET (p_tx_curr_desc, queue);
  1320. MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
  1321. (eth_port_num)
  1322. + (4 * queue)),
  1323. ((unsigned int) p_tx_curr_desc));
  1324. }
  1325. /* Assignment of Rx CRDP of given queue */
  1326. for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
  1327. CURR_RFD_GET (p_rx_curr_desc, queue);
  1328. MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
  1329. (eth_port_num)
  1330. + (4 * queue)),
  1331. ((unsigned int) p_rx_curr_desc));
  1332. if (p_rx_curr_desc != NULL)
  1333. /* Add the assigned Ethernet address to the port's address table */
  1334. eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
  1335. p_eth_port_ctrl->port_mac_addr,
  1336. queue);
  1337. }
  1338. /* Assign port configuration and command. */
  1339. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
  1340. p_eth_port_ctrl->port_config);
  1341. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
  1342. p_eth_port_ctrl->port_config_extend);
  1343. MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1344. p_eth_port_ctrl->port_serial_control);
  1345. MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1346. ETH_SERIAL_PORT_ENABLE);
  1347. /* Assign port SDMA configuration */
  1348. MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
  1349. p_eth_port_ctrl->port_sdma_config);
  1350. MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
  1351. (eth_port_num), 0x3fffffff);
  1352. MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
  1353. (eth_port_num), 0x03fffcff);
  1354. /* Turn off the port/queue bandwidth limitation */
  1355. MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
  1356. /* Enable port Rx. */
  1357. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
  1358. p_eth_port_ctrl->port_rx_queue_command);
  1359. /* Check if link is up */
  1360. eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
  1361. if (!(phy_reg_data & 0x20))
  1362. return false;
  1363. return true;
  1364. }
  1365. /*******************************************************************************
  1366. * eth_port_uc_addr_set - This function Set the port Unicast address.
  1367. *
  1368. * DESCRIPTION:
  1369. * This function Set the port Ethernet MAC address.
  1370. *
  1371. * INPUT:
  1372. * ETH_PORT eth_port_num Port number.
  1373. * char * p_addr Address to be set
  1374. * ETH_QUEUE queue Rx queue number for this MAC address.
  1375. *
  1376. * OUTPUT:
  1377. * Set MAC address low and high registers. also calls eth_port_uc_addr()
  1378. * To set the unicast table with the proper information.
  1379. *
  1380. * RETURN:
  1381. * N/A.
  1382. *
  1383. *******************************************************************************/
  1384. static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
  1385. unsigned char *p_addr, ETH_QUEUE queue)
  1386. {
  1387. unsigned int mac_h;
  1388. unsigned int mac_l;
  1389. mac_l = (p_addr[4] << 8) | (p_addr[5]);
  1390. mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
  1391. (p_addr[2] << 8) | (p_addr[3] << 0);
  1392. MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
  1393. MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
  1394. /* Accept frames of this address */
  1395. eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
  1396. return;
  1397. }
  1398. /*******************************************************************************
  1399. * eth_port_uc_addr - This function Set the port unicast address table
  1400. *
  1401. * DESCRIPTION:
  1402. * This function locates the proper entry in the Unicast table for the
  1403. * specified MAC nibble and sets its properties according to function
  1404. * parameters.
  1405. *
  1406. * INPUT:
  1407. * ETH_PORT eth_port_num Port number.
  1408. * unsigned char uc_nibble Unicast MAC Address last nibble.
  1409. * ETH_QUEUE queue Rx queue number for this MAC address.
  1410. * int option 0 = Add, 1 = remove address.
  1411. *
  1412. * OUTPUT:
  1413. * This function add/removes MAC addresses from the port unicast address
  1414. * table.
  1415. *
  1416. * RETURN:
  1417. * true is output succeeded.
  1418. * false if option parameter is invalid.
  1419. *
  1420. *******************************************************************************/
  1421. static bool eth_port_uc_addr (ETH_PORT eth_port_num,
  1422. unsigned char uc_nibble,
  1423. ETH_QUEUE queue, int option)
  1424. {
  1425. unsigned int unicast_reg;
  1426. unsigned int tbl_offset;
  1427. unsigned int reg_offset;
  1428. /* Locate the Unicast table entry */
  1429. uc_nibble = (0xf & uc_nibble);
  1430. tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
  1431. reg_offset = uc_nibble % 4; /* Entry offset within the above register */
  1432. switch (option) {
  1433. case REJECT_MAC_ADDR:
  1434. /* Clear accepts frame bit at specified unicast DA table entry */
  1435. unicast_reg =
  1436. MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1437. (eth_port_num)
  1438. + tbl_offset));
  1439. unicast_reg &= (0x0E << (8 * reg_offset));
  1440. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1441. (eth_port_num)
  1442. + tbl_offset), unicast_reg);
  1443. break;
  1444. case ACCEPT_MAC_ADDR:
  1445. /* Set accepts frame bit at unicast DA filter table entry */
  1446. unicast_reg =
  1447. MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1448. (eth_port_num)
  1449. + tbl_offset));
  1450. unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
  1451. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1452. (eth_port_num)
  1453. + tbl_offset), unicast_reg);
  1454. break;
  1455. default:
  1456. return false;
  1457. }
  1458. return true;
  1459. }
  1460. #if 0 /* FIXME */
  1461. /*******************************************************************************
  1462. * eth_port_mc_addr - Multicast address settings.
  1463. *
  1464. * DESCRIPTION:
  1465. * This API controls the MV device MAC multicast support.
  1466. * The MV device supports multicast using two tables:
  1467. * 1) Special Multicast Table for MAC addresses of the form
  1468. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
  1469. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1470. * Table entries in the DA-Filter table.
  1471. * In this case, the function calls eth_port_smc_addr() routine to set the
  1472. * Special Multicast Table.
  1473. * 2) Other Multicast Table for multicast of another type. A CRC-8bit
  1474. * is used as an index to the Other Multicast Table entries in the
  1475. * DA-Filter table.
  1476. * In this case, the function calculates the CRC-8bit value and calls
  1477. * eth_port_omc_addr() routine to set the Other Multicast Table.
  1478. * INPUT:
  1479. * ETH_PORT eth_port_num Port number.
  1480. * unsigned char *p_addr Unicast MAC Address.
  1481. * ETH_QUEUE queue Rx queue number for this MAC address.
  1482. * int option 0 = Add, 1 = remove address.
  1483. *
  1484. * OUTPUT:
  1485. * See description.
  1486. *
  1487. * RETURN:
  1488. * true is output succeeded.
  1489. * false if add_address_table_entry( ) failed.
  1490. *
  1491. *******************************************************************************/
  1492. static void eth_port_mc_addr (ETH_PORT eth_port_num,
  1493. unsigned char *p_addr,
  1494. ETH_QUEUE queue, int option)
  1495. {
  1496. unsigned int mac_h;
  1497. unsigned int mac_l;
  1498. unsigned char crc_result = 0;
  1499. int mac_array[48];
  1500. int crc[8];
  1501. int i;
  1502. if ((p_addr[0] == 0x01) &&
  1503. (p_addr[1] == 0x00) &&
  1504. (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
  1505. eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
  1506. else {
  1507. /* Calculate CRC-8 out of the given address */
  1508. mac_h = (p_addr[0] << 8) | (p_addr[1]);
  1509. mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
  1510. (p_addr[4] << 8) | (p_addr[5] << 0);
  1511. for (i = 0; i < 32; i++)
  1512. mac_array[i] = (mac_l >> i) & 0x1;
  1513. for (i = 32; i < 48; i++)
  1514. mac_array[i] = (mac_h >> (i - 32)) & 0x1;
  1515. crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
  1516. mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
  1517. mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
  1518. mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
  1519. mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
  1520. mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
  1521. mac_array[6] ^ mac_array[0];
  1522. crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
  1523. mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
  1524. mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
  1525. mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
  1526. mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
  1527. mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
  1528. mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
  1529. mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
  1530. mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
  1531. mac_array[0];
  1532. crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
  1533. mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
  1534. mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
  1535. mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
  1536. mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
  1537. mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
  1538. mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
  1539. mac_array[2] ^ mac_array[1] ^ mac_array[0];
  1540. crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
  1541. mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
  1542. mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
  1543. mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
  1544. mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
  1545. mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
  1546. mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
  1547. mac_array[2] ^ mac_array[1];
  1548. crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
  1549. mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
  1550. mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
  1551. mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
  1552. mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
  1553. mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
  1554. mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
  1555. mac_array[2];
  1556. crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
  1557. mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
  1558. mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
  1559. mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
  1560. mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
  1561. mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
  1562. mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
  1563. mac_array[3];
  1564. crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
  1565. mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
  1566. mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
  1567. mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
  1568. mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
  1569. mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
  1570. mac_array[6] ^ mac_array[5] ^ mac_array[4];
  1571. crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
  1572. mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
  1573. mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
  1574. mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
  1575. mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
  1576. mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
  1577. mac_array[6] ^ mac_array[5];
  1578. for (i = 0; i < 8; i++)
  1579. crc_result = crc_result | (crc[i] << i);
  1580. eth_port_omc_addr (eth_port_num, crc_result, queue, option);
  1581. }
  1582. return;
  1583. }
  1584. /*******************************************************************************
  1585. * eth_port_smc_addr - Special Multicast address settings.
  1586. *
  1587. * DESCRIPTION:
  1588. * This routine controls the MV device special MAC multicast support.
  1589. * The Special Multicast Table for MAC addresses supports MAC of the form
  1590. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
  1591. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1592. * Table entries in the DA-Filter table.
  1593. * This function set the Special Multicast Table appropriate entry
  1594. * according to the argument given.
  1595. *
  1596. * INPUT:
  1597. * ETH_PORT eth_port_num Port number.
  1598. * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
  1599. * ETH_QUEUE queue Rx queue number for this MAC address.
  1600. * int option 0 = Add, 1 = remove address.
  1601. *
  1602. * OUTPUT:
  1603. * See description.
  1604. *
  1605. * RETURN:
  1606. * true is output succeeded.
  1607. * false if option parameter is invalid.
  1608. *
  1609. *******************************************************************************/
  1610. static bool eth_port_smc_addr (ETH_PORT eth_port_num,
  1611. unsigned char mc_byte,
  1612. ETH_QUEUE queue, int option)
  1613. {
  1614. unsigned int smc_table_reg;
  1615. unsigned int tbl_offset;
  1616. unsigned int reg_offset;
  1617. /* Locate the SMC table entry */
  1618. tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
  1619. reg_offset = mc_byte % 4; /* Entry offset within the above register */
  1620. queue &= 0x7;
  1621. switch (option) {
  1622. case REJECT_MAC_ADDR:
  1623. /* Clear accepts frame bit at specified Special DA table entry */
  1624. smc_table_reg =
  1625. MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1626. smc_table_reg &= (0x0E << (8 * reg_offset));
  1627. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
  1628. break;
  1629. case ACCEPT_MAC_ADDR:
  1630. /* Set accepts frame bit at specified Special DA table entry */
  1631. smc_table_reg =
  1632. MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1633. smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
  1634. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
  1635. break;
  1636. default:
  1637. return false;
  1638. }
  1639. return true;
  1640. }
  1641. /*******************************************************************************
  1642. * eth_port_omc_addr - Multicast address settings.
  1643. *
  1644. * DESCRIPTION:
  1645. * This routine controls the MV device Other MAC multicast support.
  1646. * The Other Multicast Table is used for multicast of another type.
  1647. * A CRC-8bit is used as an index to the Other Multicast Table entries
  1648. * in the DA-Filter table.
  1649. * The function gets the CRC-8bit value from the calling routine and
  1650. * set the Other Multicast Table appropriate entry according to the
  1651. * CRC-8 argument given.
  1652. *
  1653. * INPUT:
  1654. * ETH_PORT eth_port_num Port number.
  1655. * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
  1656. * ETH_QUEUE queue Rx queue number for this MAC address.
  1657. * int option 0 = Add, 1 = remove address.
  1658. *
  1659. * OUTPUT:
  1660. * See description.
  1661. *
  1662. * RETURN:
  1663. * true is output succeeded.
  1664. * false if option parameter is invalid.
  1665. *
  1666. *******************************************************************************/
  1667. static bool eth_port_omc_addr (ETH_PORT eth_port_num,
  1668. unsigned char crc8,
  1669. ETH_QUEUE queue, int option)
  1670. {
  1671. unsigned int omc_table_reg;
  1672. unsigned int tbl_offset;
  1673. unsigned int reg_offset;
  1674. /* Locate the OMC table entry */
  1675. tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
  1676. reg_offset = crc8 % 4; /* Entry offset within the above register */
  1677. queue &= 0x7;
  1678. switch (option) {
  1679. case REJECT_MAC_ADDR:
  1680. /* Clear accepts frame bit at specified Other DA table entry */
  1681. omc_table_reg =
  1682. MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1683. omc_table_reg &= (0x0E << (8 * reg_offset));
  1684. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
  1685. break;
  1686. case ACCEPT_MAC_ADDR:
  1687. /* Set accepts frame bit at specified Other DA table entry */
  1688. omc_table_reg =
  1689. MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1690. omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
  1691. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
  1692. break;
  1693. default:
  1694. return false;
  1695. }
  1696. return true;
  1697. }
  1698. #endif
  1699. /*******************************************************************************
  1700. * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
  1701. *
  1702. * DESCRIPTION:
  1703. * Go through all the DA filter tables (Unicast, Special Multicast & Other
  1704. * Multicast) and set each entry to 0.
  1705. *
  1706. * INPUT:
  1707. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1708. *
  1709. * OUTPUT:
  1710. * Multicast and Unicast packets are rejected.
  1711. *
  1712. * RETURN:
  1713. * None.
  1714. *
  1715. *******************************************************************************/
  1716. static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
  1717. {
  1718. int table_index;
  1719. /* Clear DA filter unicast table (Ex_dFUT) */
  1720. for (table_index = 0; table_index <= 0xC; table_index += 4)
  1721. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1722. (eth_port_num) + table_index), 0);
  1723. for (table_index = 0; table_index <= 0xFC; table_index += 4) {
  1724. /* Clear DA filter special multicast table (Ex_dFSMT) */
  1725. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
  1726. /* Clear DA filter other multicast table (Ex_dFOMT) */
  1727. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
  1728. }
  1729. }
  1730. /*******************************************************************************
  1731. * eth_clear_mib_counters - Clear all MIB counters
  1732. *
  1733. * DESCRIPTION:
  1734. * This function clears all MIB counters of a specific ethernet port.
  1735. * A read from the MIB counter will reset the counter.
  1736. *
  1737. * INPUT:
  1738. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1739. *
  1740. * OUTPUT:
  1741. * After reading all MIB counters, the counters resets.
  1742. *
  1743. * RETURN:
  1744. * MIB counter value.
  1745. *
  1746. *******************************************************************************/
  1747. static void eth_clear_mib_counters (ETH_PORT eth_port_num)
  1748. {
  1749. int i;
  1750. /* Perform dummy reads from MIB counters */
  1751. for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
  1752. i += 4) {
  1753. (void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
  1754. (eth_port_num) + i));
  1755. }
  1756. return;
  1757. }
  1758. /*******************************************************************************
  1759. * eth_read_mib_counter - Read a MIB counter
  1760. *
  1761. * DESCRIPTION:
  1762. * This function reads a MIB counter of a specific ethernet port.
  1763. * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
  1764. * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
  1765. * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
  1766. * ETH_MIB_GOOD_OCTETS_SENT_HIGH
  1767. *
  1768. * INPUT:
  1769. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1770. * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
  1771. *
  1772. * OUTPUT:
  1773. * After reading the MIB counter, the counter resets.
  1774. *
  1775. * RETURN:
  1776. * MIB counter value.
  1777. *
  1778. *******************************************************************************/
  1779. unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
  1780. unsigned int mib_offset)
  1781. {
  1782. return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
  1783. + mib_offset));
  1784. }
  1785. /*******************************************************************************
  1786. * ethernet_phy_set - Set the ethernet port PHY address.
  1787. *
  1788. * DESCRIPTION:
  1789. * This routine set the ethernet port PHY address according to given
  1790. * parameter.
  1791. *
  1792. * INPUT:
  1793. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1794. *
  1795. * OUTPUT:
  1796. * Set PHY Address Register with given PHY address parameter.
  1797. *
  1798. * RETURN:
  1799. * None.
  1800. *
  1801. *******************************************************************************/
  1802. static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
  1803. {
  1804. unsigned int reg_data;
  1805. reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
  1806. reg_data &= ~(0x1F << (5 * eth_port_num));
  1807. reg_data |= (phy_addr << (5 * eth_port_num));
  1808. MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
  1809. return;
  1810. }
  1811. /*******************************************************************************
  1812. * ethernet_phy_get - Get the ethernet port PHY address.
  1813. *
  1814. * DESCRIPTION:
  1815. * This routine returns the given ethernet port PHY address.
  1816. *
  1817. * INPUT:
  1818. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1819. *
  1820. * OUTPUT:
  1821. * None.
  1822. *
  1823. * RETURN:
  1824. * PHY address.
  1825. *
  1826. *******************************************************************************/
  1827. static int ethernet_phy_get (ETH_PORT eth_port_num)
  1828. {
  1829. unsigned int reg_data;
  1830. reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
  1831. return ((reg_data >> (5 * eth_port_num)) & 0x1f);
  1832. }
  1833. /*******************************************************************************
  1834. * ethernet_phy_reset - Reset Ethernet port PHY.
  1835. *
  1836. * DESCRIPTION:
  1837. * This routine utilize the SMI interface to reset the ethernet port PHY.
  1838. * The routine waits until the link is up again or link up is timeout.
  1839. *
  1840. * INPUT:
  1841. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1842. *
  1843. * OUTPUT:
  1844. * The ethernet port PHY renew its link.
  1845. *
  1846. * RETURN:
  1847. * None.
  1848. *
  1849. *******************************************************************************/
  1850. static bool ethernet_phy_reset (ETH_PORT eth_port_num)
  1851. {
  1852. unsigned int time_out = 50;
  1853. unsigned int phy_reg_data;
  1854. /* Reset the PHY */
  1855. eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
  1856. phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
  1857. eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
  1858. /* Poll on the PHY LINK */
  1859. do {
  1860. eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
  1861. if (time_out-- == 0)
  1862. return false;
  1863. }
  1864. while (!(phy_reg_data & 0x20));
  1865. return true;
  1866. }
  1867. /*******************************************************************************
  1868. * eth_port_reset - Reset Ethernet port
  1869. *
  1870. * DESCRIPTION:
  1871. * This routine resets the chip by aborting any SDMA engine activity and
  1872. * clearing the MIB counters. The Receiver and the Transmit unit are in
  1873. * idle state after this command is performed and the port is disabled.
  1874. *
  1875. * INPUT:
  1876. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1877. *
  1878. * OUTPUT:
  1879. * Channel activity is halted.
  1880. *
  1881. * RETURN:
  1882. * None.
  1883. *
  1884. *******************************************************************************/
  1885. static void eth_port_reset (ETH_PORT eth_port_num)
  1886. {
  1887. unsigned int reg_data;
  1888. /* Stop Tx port activity. Check port Tx activity. */
  1889. reg_data =
  1890. MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1891. (eth_port_num));
  1892. if (reg_data & 0xFF) {
  1893. /* Issue stop command for active channels only */
  1894. MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1895. (eth_port_num), (reg_data << 8));
  1896. /* Wait for all Tx activity to terminate. */
  1897. do {
  1898. /* Check port cause register that all Tx queues are stopped */
  1899. reg_data =
  1900. MV_REG_READ
  1901. (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1902. (eth_port_num));
  1903. }
  1904. while (reg_data & 0xFF);
  1905. }
  1906. /* Stop Rx port activity. Check port Rx activity. */
  1907. reg_data =
  1908. MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
  1909. (eth_port_num));
  1910. if (reg_data & 0xFF) {
  1911. /* Issue stop command for active channels only */
  1912. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
  1913. (eth_port_num), (reg_data << 8));
  1914. /* Wait for all Rx activity to terminate. */
  1915. do {
  1916. /* Check port cause register that all Rx queues are stopped */
  1917. reg_data =
  1918. MV_REG_READ
  1919. (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
  1920. (eth_port_num));
  1921. }
  1922. while (reg_data & 0xFF);
  1923. }
  1924. /* Clear all MIB counters */
  1925. eth_clear_mib_counters (eth_port_num);
  1926. /* Reset the Enable bit in the Configuration Register */
  1927. reg_data =
  1928. MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
  1929. (eth_port_num));
  1930. reg_data &= ~ETH_SERIAL_PORT_ENABLE;
  1931. MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1932. reg_data);
  1933. return;
  1934. }
  1935. #if 0 /* Not needed here */
  1936. /*******************************************************************************
  1937. * ethernet_set_config_reg - Set specified bits in configuration register.
  1938. *
  1939. * DESCRIPTION:
  1940. * This function sets specified bits in the given ethernet
  1941. * configuration register.
  1942. *
  1943. * INPUT:
  1944. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1945. * unsigned int value 32 bit value.
  1946. *
  1947. * OUTPUT:
  1948. * The set bits in the value parameter are set in the configuration
  1949. * register.
  1950. *
  1951. * RETURN:
  1952. * None.
  1953. *
  1954. *******************************************************************************/
  1955. static void ethernet_set_config_reg (ETH_PORT eth_port_num,
  1956. unsigned int value)
  1957. {
  1958. unsigned int eth_config_reg;
  1959. eth_config_reg =
  1960. MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
  1961. eth_config_reg |= value;
  1962. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
  1963. eth_config_reg);
  1964. return;
  1965. }
  1966. #endif
  1967. #if 0 /* FIXME */
  1968. /*******************************************************************************
  1969. * ethernet_reset_config_reg - Reset specified bits in configuration register.
  1970. *
  1971. * DESCRIPTION:
  1972. * This function resets specified bits in the given Ethernet
  1973. * configuration register.
  1974. *
  1975. * INPUT:
  1976. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1977. * unsigned int value 32 bit value.
  1978. *
  1979. * OUTPUT:
  1980. * The set bits in the value parameter are reset in the configuration
  1981. * register.
  1982. *
  1983. * RETURN:
  1984. * None.
  1985. *
  1986. *******************************************************************************/
  1987. static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
  1988. unsigned int value)
  1989. {
  1990. unsigned int eth_config_reg;
  1991. eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
  1992. (eth_port_num));
  1993. eth_config_reg &= ~value;
  1994. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
  1995. eth_config_reg);
  1996. return;
  1997. }
  1998. #endif
  1999. #if 0 /* Not needed here */
  2000. /*******************************************************************************
  2001. * ethernet_get_config_reg - Get the port configuration register
  2002. *
  2003. * DESCRIPTION:
  2004. * This function returns the configuration register value of the given
  2005. * ethernet port.
  2006. *
  2007. * INPUT:
  2008. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2009. *
  2010. * OUTPUT:
  2011. * None.
  2012. *
  2013. * RETURN:
  2014. * Port configuration register value.
  2015. *
  2016. *******************************************************************************/
  2017. static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
  2018. {
  2019. unsigned int eth_config_reg;
  2020. eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
  2021. (eth_port_num));
  2022. return eth_config_reg;
  2023. }
  2024. #endif
  2025. /*******************************************************************************
  2026. * eth_port_read_smi_reg - Read PHY registers
  2027. *
  2028. * DESCRIPTION:
  2029. * This routine utilize the SMI interface to interact with the PHY in
  2030. * order to perform PHY register read.
  2031. *
  2032. * INPUT:
  2033. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2034. * unsigned int phy_reg PHY register address offset.
  2035. * unsigned int *value Register value buffer.
  2036. *
  2037. * OUTPUT:
  2038. * Write the value of a specified PHY register into given buffer.
  2039. *
  2040. * RETURN:
  2041. * false if the PHY is busy or read data is not in valid state.
  2042. * true otherwise.
  2043. *
  2044. *******************************************************************************/
  2045. static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
  2046. unsigned int phy_reg, unsigned int *value)
  2047. {
  2048. unsigned int reg_value;
  2049. unsigned int time_out = PHY_BUSY_TIMEOUT;
  2050. int phy_addr;
  2051. phy_addr = ethernet_phy_get (eth_port_num);
  2052. /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
  2053. /* first check that it is not busy */
  2054. do {
  2055. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2056. if (time_out-- == 0) {
  2057. return false;
  2058. }
  2059. }
  2060. while (reg_value & ETH_SMI_BUSY);
  2061. /* not busy */
  2062. MV_REG_WRITE (MV64360_ETH_SMI_REG,
  2063. (phy_addr << 16) | (phy_reg << 21) |
  2064. ETH_SMI_OPCODE_READ);
  2065. time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
  2066. do {
  2067. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2068. if (time_out-- == 0) {
  2069. return false;
  2070. }
  2071. }
  2072. while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
  2073. /* Wait for the data to update in the SMI register */
  2074. #define PHY_UPDATE_TIMEOUT 10000
  2075. for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
  2076. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2077. *value = reg_value & 0xffff;
  2078. return true;
  2079. }
  2080. /*******************************************************************************
  2081. * eth_port_write_smi_reg - Write to PHY registers
  2082. *
  2083. * DESCRIPTION:
  2084. * This routine utilize the SMI interface to interact with the PHY in
  2085. * order to perform writes to PHY registers.
  2086. *
  2087. * INPUT:
  2088. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2089. * unsigned int phy_reg PHY register address offset.
  2090. * unsigned int value Register value.
  2091. *
  2092. * OUTPUT:
  2093. * Write the given value to the specified PHY register.
  2094. *
  2095. * RETURN:
  2096. * false if the PHY is busy.
  2097. * true otherwise.
  2098. *
  2099. *******************************************************************************/
  2100. static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
  2101. unsigned int phy_reg, unsigned int value)
  2102. {
  2103. unsigned int reg_value;
  2104. unsigned int time_out = PHY_BUSY_TIMEOUT;
  2105. int phy_addr;
  2106. phy_addr = ethernet_phy_get (eth_port_num);
  2107. /* first check that it is not busy */
  2108. do {
  2109. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2110. if (time_out-- == 0) {
  2111. return false;
  2112. }
  2113. }
  2114. while (reg_value & ETH_SMI_BUSY);
  2115. /* not busy */
  2116. MV_REG_WRITE (MV64360_ETH_SMI_REG,
  2117. (phy_addr << 16) | (phy_reg << 21) |
  2118. ETH_SMI_OPCODE_WRITE | (value & 0xffff));
  2119. return true;
  2120. }
  2121. /*******************************************************************************
  2122. * eth_set_access_control - Config address decode parameters for Ethernet unit
  2123. *
  2124. * DESCRIPTION:
  2125. * This function configures the address decode parameters for the Gigabit
  2126. * Ethernet Controller according the given parameters struct.
  2127. *
  2128. * INPUT:
  2129. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2130. * ETH_WIN_PARAM *param Address decode parameter struct.
  2131. *
  2132. * OUTPUT:
  2133. * An access window is opened using the given access parameters.
  2134. *
  2135. * RETURN:
  2136. * None.
  2137. *
  2138. *******************************************************************************/
  2139. static void eth_set_access_control (ETH_PORT eth_port_num,
  2140. ETH_WIN_PARAM * param)
  2141. {
  2142. unsigned int access_prot_reg;
  2143. /* Set access control register */
  2144. access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
  2145. (eth_port_num));
  2146. access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
  2147. access_prot_reg |= (param->access_ctrl << (param->win * 2));
  2148. MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
  2149. access_prot_reg);
  2150. /* Set window Size reg (SR) */
  2151. MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
  2152. (ETH_SIZE_REG_GAP * param->win)),
  2153. (((param->size / 0x10000) - 1) << 16));
  2154. /* Set window Base address reg (BA) */
  2155. MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
  2156. (param->target | param->attributes | param->base_addr));
  2157. /* High address remap reg (HARR) */
  2158. if (param->win < 4)
  2159. MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
  2160. (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
  2161. param->high_addr);
  2162. /* Base address enable reg (BARER) */
  2163. if (param->enable == 1)
  2164. MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
  2165. (1 << param->win));
  2166. else
  2167. MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
  2168. (1 << param->win));
  2169. }
  2170. /*******************************************************************************
  2171. * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
  2172. *
  2173. * DESCRIPTION:
  2174. * This function prepares a Rx chained list of descriptors and packet
  2175. * buffers in a form of a ring. The routine must be called after port
  2176. * initialization routine and before port start routine.
  2177. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  2178. * devices in the system (i.e. DRAM). This function uses the ethernet
  2179. * struct 'virtual to physical' routine (set by the user) to set the ring
  2180. * with physical addresses.
  2181. *
  2182. * INPUT:
  2183. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2184. * ETH_QUEUE rx_queue Number of Rx queue.
  2185. * int rx_desc_num Number of Rx descriptors
  2186. * int rx_buff_size Size of Rx buffer
  2187. * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
  2188. * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
  2189. *
  2190. * OUTPUT:
  2191. * The routine updates the Ethernet port control struct with information
  2192. * regarding the Rx descriptors and buffers.
  2193. *
  2194. * RETURN:
  2195. * false if the given descriptors memory area is not aligned according to
  2196. * Ethernet SDMA specifications.
  2197. * true otherwise.
  2198. *
  2199. *******************************************************************************/
  2200. static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  2201. ETH_QUEUE rx_queue,
  2202. int rx_desc_num,
  2203. int rx_buff_size,
  2204. unsigned int rx_desc_base_addr,
  2205. unsigned int rx_buff_base_addr)
  2206. {
  2207. ETH_RX_DESC *p_rx_desc;
  2208. ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
  2209. unsigned int buffer_addr;
  2210. int ix; /* a counter */
  2211. p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
  2212. p_rx_prev_desc = p_rx_desc;
  2213. buffer_addr = rx_buff_base_addr;
  2214. /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
  2215. if (rx_buff_base_addr & 0xF)
  2216. return false;
  2217. /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
  2218. if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
  2219. return false;
  2220. /* Rx buffers must be 64-bit aligned. */
  2221. if ((rx_buff_base_addr + rx_buff_size) & 0x7)
  2222. return false;
  2223. /* initialize the Rx descriptors ring */
  2224. for (ix = 0; ix < rx_desc_num; ix++) {
  2225. p_rx_desc->buf_size = rx_buff_size;
  2226. p_rx_desc->byte_cnt = 0x0000;
  2227. p_rx_desc->cmd_sts =
  2228. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2229. p_rx_desc->next_desc_ptr =
  2230. ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
  2231. p_rx_desc->buf_ptr = buffer_addr;
  2232. p_rx_desc->return_info = 0x00000000;
  2233. D_CACHE_FLUSH_LINE (p_rx_desc, 0);
  2234. buffer_addr += rx_buff_size;
  2235. p_rx_prev_desc = p_rx_desc;
  2236. p_rx_desc = (ETH_RX_DESC *)
  2237. ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
  2238. }
  2239. /* Closing Rx descriptors ring */
  2240. p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
  2241. D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
  2242. /* Save Rx desc pointer to driver struct. */
  2243. CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
  2244. USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
  2245. p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
  2246. (ETH_RX_DESC *) rx_desc_base_addr;
  2247. p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
  2248. rx_desc_num * RX_DESC_ALIGNED_SIZE;
  2249. p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
  2250. return true;
  2251. }
  2252. /*******************************************************************************
  2253. * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
  2254. *
  2255. * DESCRIPTION:
  2256. * This function prepares a Tx chained list of descriptors and packet
  2257. * buffers in a form of a ring. The routine must be called after port
  2258. * initialization routine and before port start routine.
  2259. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  2260. * devices in the system (i.e. DRAM). This function uses the ethernet
  2261. * struct 'virtual to physical' routine (set by the user) to set the ring
  2262. * with physical addresses.
  2263. *
  2264. * INPUT:
  2265. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2266. * ETH_QUEUE tx_queue Number of Tx queue.
  2267. * int tx_desc_num Number of Tx descriptors
  2268. * int tx_buff_size Size of Tx buffer
  2269. * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
  2270. * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
  2271. *
  2272. * OUTPUT:
  2273. * The routine updates the Ethernet port control struct with information
  2274. * regarding the Tx descriptors and buffers.
  2275. *
  2276. * RETURN:
  2277. * false if the given descriptors memory area is not aligned according to
  2278. * Ethernet SDMA specifications.
  2279. * true otherwise.
  2280. *
  2281. *******************************************************************************/
  2282. static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  2283. ETH_QUEUE tx_queue,
  2284. int tx_desc_num,
  2285. int tx_buff_size,
  2286. unsigned int tx_desc_base_addr,
  2287. unsigned int tx_buff_base_addr)
  2288. {
  2289. ETH_TX_DESC *p_tx_desc;
  2290. ETH_TX_DESC *p_tx_prev_desc;
  2291. unsigned int buffer_addr;
  2292. int ix; /* a counter */
  2293. /* save the first desc pointer to link with the last descriptor */
  2294. p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
  2295. p_tx_prev_desc = p_tx_desc;
  2296. buffer_addr = tx_buff_base_addr;
  2297. /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
  2298. if (tx_buff_base_addr & 0xF)
  2299. return false;
  2300. /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
  2301. if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
  2302. || (tx_buff_size < TX_BUFFER_MIN_SIZE))
  2303. return false;
  2304. /* Initialize the Tx descriptors ring */
  2305. for (ix = 0; ix < tx_desc_num; ix++) {
  2306. p_tx_desc->byte_cnt = 0x0000;
  2307. p_tx_desc->l4i_chk = 0x0000;
  2308. p_tx_desc->cmd_sts = 0x00000000;
  2309. p_tx_desc->next_desc_ptr =
  2310. ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
  2311. p_tx_desc->buf_ptr = buffer_addr;
  2312. p_tx_desc->return_info = 0x00000000;
  2313. D_CACHE_FLUSH_LINE (p_tx_desc, 0);
  2314. buffer_addr += tx_buff_size;
  2315. p_tx_prev_desc = p_tx_desc;
  2316. p_tx_desc = (ETH_TX_DESC *)
  2317. ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
  2318. }
  2319. /* Closing Tx descriptors ring */
  2320. p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
  2321. D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
  2322. /* Set Tx desc pointer in driver struct. */
  2323. CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
  2324. USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
  2325. /* Init Tx ring base and size parameters */
  2326. p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
  2327. (ETH_TX_DESC *) tx_desc_base_addr;
  2328. p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
  2329. (tx_desc_num * TX_DESC_ALIGNED_SIZE);
  2330. /* Add the queue to the list of Tx queues of this port */
  2331. p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
  2332. return true;
  2333. }
  2334. /*******************************************************************************
  2335. * eth_port_send - Send an Ethernet packet
  2336. *
  2337. * DESCRIPTION:
  2338. * This routine send a given packet described by p_pktinfo parameter. It
  2339. * supports transmitting of a packet spaned over multiple buffers. The
  2340. * routine updates 'curr' and 'first' indexes according to the packet
  2341. * segment passed to the routine. In case the packet segment is first,
  2342. * the 'first' index is update. In any case, the 'curr' index is updated.
  2343. * If the routine get into Tx resource error it assigns 'curr' index as
  2344. * 'first'. This way the function can abort Tx process of multiple
  2345. * descriptors per packet.
  2346. *
  2347. * INPUT:
  2348. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2349. * ETH_QUEUE tx_queue Number of Tx queue.
  2350. * PKT_INFO *p_pkt_info User packet buffer.
  2351. *
  2352. * OUTPUT:
  2353. * Tx ring 'curr' and 'first' indexes are updated.
  2354. *
  2355. * RETURN:
  2356. * ETH_QUEUE_FULL in case of Tx resource error.
  2357. * ETH_ERROR in case the routine can not access Tx desc ring.
  2358. * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
  2359. * ETH_OK otherwise.
  2360. *
  2361. *******************************************************************************/
  2362. static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
  2363. ETH_QUEUE tx_queue,
  2364. PKT_INFO * p_pkt_info)
  2365. {
  2366. volatile ETH_TX_DESC *p_tx_desc_first;
  2367. volatile ETH_TX_DESC *p_tx_desc_curr;
  2368. volatile ETH_TX_DESC *p_tx_next_desc_curr;
  2369. volatile ETH_TX_DESC *p_tx_desc_used;
  2370. unsigned int command_status;
  2371. /* Do not process Tx ring in case of Tx ring resource error */
  2372. if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
  2373. return ETH_QUEUE_FULL;
  2374. /* Get the Tx Desc ring indexes */
  2375. CURR_TFD_GET (p_tx_desc_curr, tx_queue);
  2376. USED_TFD_GET (p_tx_desc_used, tx_queue);
  2377. if (p_tx_desc_curr == NULL)
  2378. return ETH_ERROR;
  2379. /* The following parameters are used to save readings from memory */
  2380. p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
  2381. command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
  2382. if (command_status & (ETH_TX_FIRST_DESC)) {
  2383. /* Update first desc */
  2384. FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
  2385. p_tx_desc_first = p_tx_desc_curr;
  2386. } else {
  2387. FIRST_TFD_GET (p_tx_desc_first, tx_queue);
  2388. command_status |= ETH_BUFFER_OWNED_BY_DMA;
  2389. }
  2390. /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
  2391. /* boundary. We use the memory allocated for Tx descriptor. This memory */
  2392. /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
  2393. if (p_pkt_info->byte_cnt <= 8) {
  2394. printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
  2395. return ETH_ERROR;
  2396. p_tx_desc_curr->buf_ptr =
  2397. (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
  2398. eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
  2399. p_pkt_info->byte_cnt);
  2400. } else
  2401. p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
  2402. p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
  2403. p_tx_desc_curr->return_info = p_pkt_info->return_info;
  2404. if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
  2405. /* Set last desc with DMA ownership and interrupt enable. */
  2406. p_tx_desc_curr->cmd_sts = command_status |
  2407. ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
  2408. if (p_tx_desc_curr != p_tx_desc_first)
  2409. p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
  2410. /* Flush CPU pipe */
  2411. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
  2412. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
  2413. CPU_PIPE_FLUSH;
  2414. /* Apply send command */
  2415. ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
  2416. /* Finish Tx packet. Update first desc in case of Tx resource error */
  2417. p_tx_desc_first = p_tx_next_desc_curr;
  2418. FIRST_TFD_SET (p_tx_desc_first, tx_queue);
  2419. } else {
  2420. p_tx_desc_curr->cmd_sts = command_status;
  2421. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
  2422. }
  2423. /* Check for ring index overlap in the Tx desc ring */
  2424. if (p_tx_next_desc_curr == p_tx_desc_used) {
  2425. /* Update the current descriptor */
  2426. CURR_TFD_SET (p_tx_desc_first, tx_queue);
  2427. p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
  2428. return ETH_QUEUE_LAST_RESOURCE;
  2429. } else {
  2430. /* Update the current descriptor */
  2431. CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
  2432. return ETH_OK;
  2433. }
  2434. }
  2435. /*******************************************************************************
  2436. * eth_tx_return_desc - Free all used Tx descriptors
  2437. *
  2438. * DESCRIPTION:
  2439. * This routine returns the transmitted packet information to the caller.
  2440. * It uses the 'first' index to support Tx desc return in case a transmit
  2441. * of a packet spanned over multiple buffer still in process.
  2442. * In case the Tx queue was in "resource error" condition, where there are
  2443. * no available Tx resources, the function resets the resource error flag.
  2444. *
  2445. * INPUT:
  2446. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2447. * ETH_QUEUE tx_queue Number of Tx queue.
  2448. * PKT_INFO *p_pkt_info User packet buffer.
  2449. *
  2450. * OUTPUT:
  2451. * Tx ring 'first' and 'used' indexes are updated.
  2452. *
  2453. * RETURN:
  2454. * ETH_ERROR in case the routine can not access Tx desc ring.
  2455. * ETH_RETRY in case there is transmission in process.
  2456. * ETH_END_OF_JOB if the routine has nothing to release.
  2457. * ETH_OK otherwise.
  2458. *
  2459. *******************************************************************************/
  2460. static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  2461. p_eth_port_ctrl,
  2462. ETH_QUEUE tx_queue,
  2463. PKT_INFO * p_pkt_info)
  2464. {
  2465. volatile ETH_TX_DESC *p_tx_desc_used = NULL;
  2466. volatile ETH_TX_DESC *p_tx_desc_first = NULL;
  2467. unsigned int command_status;
  2468. /* Get the Tx Desc ring indexes */
  2469. USED_TFD_GET (p_tx_desc_used, tx_queue);
  2470. FIRST_TFD_GET (p_tx_desc_first, tx_queue);
  2471. /* Sanity check */
  2472. if (p_tx_desc_used == NULL)
  2473. return ETH_ERROR;
  2474. command_status = p_tx_desc_used->cmd_sts;
  2475. /* Still transmitting... */
  2476. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2477. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2478. return ETH_RETRY;
  2479. }
  2480. /* Stop release. About to overlap the current available Tx descriptor */
  2481. if ((p_tx_desc_used == p_tx_desc_first) &&
  2482. (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
  2483. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2484. return ETH_END_OF_JOB;
  2485. }
  2486. /* Pass the packet information to the caller */
  2487. p_pkt_info->cmd_sts = command_status;
  2488. p_pkt_info->return_info = p_tx_desc_used->return_info;
  2489. p_tx_desc_used->return_info = 0;
  2490. /* Update the next descriptor to release. */
  2491. USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
  2492. /* Any Tx return cancels the Tx resource error status */
  2493. if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
  2494. p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
  2495. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2496. return ETH_OK;
  2497. }
  2498. /*******************************************************************************
  2499. * eth_port_receive - Get received information from Rx ring.
  2500. *
  2501. * DESCRIPTION:
  2502. * This routine returns the received data to the caller. There is no
  2503. * data copying during routine operation. All information is returned
  2504. * using pointer to packet information struct passed from the caller.
  2505. * If the routine exhausts Rx ring resources then the resource error flag
  2506. * is set.
  2507. *
  2508. * INPUT:
  2509. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2510. * ETH_QUEUE rx_queue Number of Rx queue.
  2511. * PKT_INFO *p_pkt_info User packet buffer.
  2512. *
  2513. * OUTPUT:
  2514. * Rx ring current and used indexes are updated.
  2515. *
  2516. * RETURN:
  2517. * ETH_ERROR in case the routine can not access Rx desc ring.
  2518. * ETH_QUEUE_FULL if Rx ring resources are exhausted.
  2519. * ETH_END_OF_JOB if there is no received data.
  2520. * ETH_OK otherwise.
  2521. *
  2522. *******************************************************************************/
  2523. static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
  2524. ETH_QUEUE rx_queue,
  2525. PKT_INFO * p_pkt_info)
  2526. {
  2527. volatile ETH_RX_DESC *p_rx_curr_desc;
  2528. volatile ETH_RX_DESC *p_rx_next_curr_desc;
  2529. volatile ETH_RX_DESC *p_rx_used_desc;
  2530. unsigned int command_status;
  2531. /* Do not process Rx ring in case of Rx ring resource error */
  2532. if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
  2533. printf ("\nRx Queue is full ...\n");
  2534. return ETH_QUEUE_FULL;
  2535. }
  2536. /* Get the Rx Desc ring 'curr and 'used' indexes */
  2537. CURR_RFD_GET (p_rx_curr_desc, rx_queue);
  2538. USED_RFD_GET (p_rx_used_desc, rx_queue);
  2539. /* Sanity check */
  2540. if (p_rx_curr_desc == NULL)
  2541. return ETH_ERROR;
  2542. /* The following parameters are used to save readings from memory */
  2543. p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
  2544. command_status = p_rx_curr_desc->cmd_sts;
  2545. /* Nothing to receive... */
  2546. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2547. /* DP(printf("Rx: command_status: %08x\n", command_status)); */
  2548. D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
  2549. /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
  2550. return ETH_END_OF_JOB;
  2551. }
  2552. p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
  2553. p_pkt_info->cmd_sts = command_status;
  2554. p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
  2555. p_pkt_info->return_info = p_rx_curr_desc->return_info;
  2556. p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
  2557. /* Clean the return info field to indicate that the packet has been */
  2558. /* moved to the upper layers */
  2559. p_rx_curr_desc->return_info = 0;
  2560. /* Update 'curr' in data structure */
  2561. CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
  2562. /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
  2563. if (p_rx_next_curr_desc == p_rx_used_desc)
  2564. p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
  2565. D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
  2566. CPU_PIPE_FLUSH;
  2567. return ETH_OK;
  2568. }
  2569. /*******************************************************************************
  2570. * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
  2571. *
  2572. * DESCRIPTION:
  2573. * This routine returns a Rx buffer back to the Rx ring. It retrieves the
  2574. * next 'used' descriptor and attached the returned buffer to it.
  2575. * In case the Rx ring was in "resource error" condition, where there are
  2576. * no available Rx resources, the function resets the resource error flag.
  2577. *
  2578. * INPUT:
  2579. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2580. * ETH_QUEUE rx_queue Number of Rx queue.
  2581. * PKT_INFO *p_pkt_info Information on the returned buffer.
  2582. *
  2583. * OUTPUT:
  2584. * New available Rx resource in Rx descriptor ring.
  2585. *
  2586. * RETURN:
  2587. * ETH_ERROR in case the routine can not access Rx desc ring.
  2588. * ETH_OK otherwise.
  2589. *
  2590. *******************************************************************************/
  2591. static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
  2592. p_eth_port_ctrl,
  2593. ETH_QUEUE rx_queue,
  2594. PKT_INFO * p_pkt_info)
  2595. {
  2596. volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
  2597. /* Get 'used' Rx descriptor */
  2598. USED_RFD_GET (p_used_rx_desc, rx_queue);
  2599. /* Sanity check */
  2600. if (p_used_rx_desc == NULL)
  2601. return ETH_ERROR;
  2602. p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
  2603. p_used_rx_desc->return_info = p_pkt_info->return_info;
  2604. p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
  2605. p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
  2606. /* Flush the write pipe */
  2607. CPU_PIPE_FLUSH;
  2608. /* Return the descriptor to DMA ownership */
  2609. p_used_rx_desc->cmd_sts =
  2610. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2611. /* Flush descriptor and CPU pipe */
  2612. D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
  2613. CPU_PIPE_FLUSH;
  2614. /* Move the used descriptor pointer to the next descriptor */
  2615. USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
  2616. /* Any Rx return cancels the Rx resource error status */
  2617. if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
  2618. p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
  2619. return ETH_OK;
  2620. }
  2621. /*******************************************************************************
  2622. * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
  2623. *
  2624. * DESCRIPTION:
  2625. * This routine sets the RX coalescing interrupt mechanism parameter.
  2626. * This parameter is a timeout counter, that counts in 64 t_clk
  2627. * chunks ; that when timeout event occurs a maskable interrupt
  2628. * occurs.
  2629. * The parameter is calculated using the tClk of the MV-643xx chip
  2630. * , and the required delay of the interrupt in usec.
  2631. *
  2632. * INPUT:
  2633. * ETH_PORT eth_port_num Ethernet port number
  2634. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  2635. * unsigned int delay Delay in usec
  2636. *
  2637. * OUTPUT:
  2638. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  2639. *
  2640. * RETURN:
  2641. * The interrupt coalescing value set in the gigE port.
  2642. *
  2643. *******************************************************************************/
  2644. #if 0 /* FIXME */
  2645. static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
  2646. unsigned int t_clk,
  2647. unsigned int delay)
  2648. {
  2649. unsigned int coal;
  2650. coal = ((t_clk / 1000000) * delay) / 64;
  2651. /* Set RX Coalescing mechanism */
  2652. MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
  2653. ((coal & 0x3fff) << 8) |
  2654. (MV_REG_READ
  2655. (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
  2656. & 0xffc000ff));
  2657. return coal;
  2658. }
  2659. #endif
  2660. /*******************************************************************************
  2661. * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
  2662. *
  2663. * DESCRIPTION:
  2664. * This routine sets the TX coalescing interrupt mechanism parameter.
  2665. * This parameter is a timeout counter, that counts in 64 t_clk
  2666. * chunks ; that when timeout event occurs a maskable interrupt
  2667. * occurs.
  2668. * The parameter is calculated using the t_cLK frequency of the
  2669. * MV-643xx chip and the required delay in the interrupt in uSec
  2670. *
  2671. * INPUT:
  2672. * ETH_PORT eth_port_num Ethernet port number
  2673. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  2674. * unsigned int delay Delay in uSeconds
  2675. *
  2676. * OUTPUT:
  2677. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  2678. *
  2679. * RETURN:
  2680. * The interrupt coalescing value set in the gigE port.
  2681. *
  2682. *******************************************************************************/
  2683. #if 0 /* FIXME */
  2684. static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
  2685. unsigned int t_clk,
  2686. unsigned int delay)
  2687. {
  2688. unsigned int coal;
  2689. coal = ((t_clk / 1000000) * delay) / 64;
  2690. /* Set TX Coalescing mechanism */
  2691. MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
  2692. coal << 4);
  2693. return coal;
  2694. }
  2695. #endif
  2696. /*******************************************************************************
  2697. * eth_b_copy - Copy bytes from source to destination
  2698. *
  2699. * DESCRIPTION:
  2700. * This function supports the eight bytes limitation on Tx buffer size.
  2701. * The routine will zero eight bytes starting from the destination address
  2702. * followed by copying bytes from the source address to the destination.
  2703. *
  2704. * INPUT:
  2705. * unsigned int src_addr 32 bit source address.
  2706. * unsigned int dst_addr 32 bit destination address.
  2707. * int byte_count Number of bytes to copy.
  2708. *
  2709. * OUTPUT:
  2710. * See description.
  2711. *
  2712. * RETURN:
  2713. * None.
  2714. *
  2715. *******************************************************************************/
  2716. static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
  2717. int byte_count)
  2718. {
  2719. /* Zero the dst_addr area */
  2720. *(unsigned int *) dst_addr = 0x0;
  2721. while (byte_count != 0) {
  2722. *(char *) dst_addr = *(char *) src_addr;
  2723. dst_addr++;
  2724. src_addr++;
  2725. byte_count--;
  2726. }
  2727. }