cpu.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <debug_uart.h>
  8. #include <environment.h>
  9. #include <misc.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/stm32.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <dm/device.h>
  14. #include <dm/uclass.h>
  15. /* RCC register */
  16. #define RCC_TZCR (STM32_RCC_BASE + 0x00)
  17. #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
  18. #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
  19. #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
  20. #define RCC_BDCR_VSWRST BIT(31)
  21. #define RCC_BDCR_RTCSRC GENMASK(17, 16)
  22. #define RCC_DBGCFGR_DBGCKEN BIT(8)
  23. /* Security register */
  24. #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
  25. #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
  26. #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
  27. #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
  28. #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
  29. #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
  30. #define PWR_CR1 (STM32_PWR_BASE + 0x00)
  31. #define PWR_CR1_DBP BIT(8)
  32. /* DBGMCU register */
  33. #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
  34. #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
  35. #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
  36. #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
  37. #define DBGMCU_IDC_DEV_ID_SHIFT 0
  38. #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
  39. #define DBGMCU_IDC_REV_ID_SHIFT 16
  40. /* boot interface from Bootrom
  41. * - boot instance = bit 31:16
  42. * - boot device = bit 15:0
  43. */
  44. #define BOOTROM_PARAM_ADDR 0x2FFC0078
  45. #define BOOTROM_MODE_MASK GENMASK(15, 0)
  46. #define BOOTROM_MODE_SHIFT 0
  47. #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
  48. #define BOOTROM_INSTANCE_SHIFT 16
  49. /* BSEC OTP index */
  50. #define BSEC_OTP_SERIAL 13
  51. #define BSEC_OTP_MAC 57
  52. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  53. static void security_init(void)
  54. {
  55. /* Disable the backup domain write protection */
  56. /* the protection is enable at each reset by hardware */
  57. /* And must be disable by software */
  58. setbits_le32(PWR_CR1, PWR_CR1_DBP);
  59. while (!(readl(PWR_CR1) & PWR_CR1_DBP))
  60. ;
  61. /* If RTC clock isn't enable so this is a cold boot then we need
  62. * to reset the backup domain
  63. */
  64. if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
  65. setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  66. while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
  67. ;
  68. clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  69. }
  70. /* allow non secure access in Write/Read for all peripheral */
  71. writel(GENMASK(25, 0), ETZPC_DECPROT0);
  72. /* Open SYSRAM for no secure access */
  73. writel(0x0, ETZPC_TZMA1_SIZE);
  74. /* enable TZC1 TZC2 clock */
  75. writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
  76. /* Region 0 set to no access by default */
  77. /* bit 0 / 16 => nsaid0 read/write Enable
  78. * bit 1 / 17 => nsaid1 read/write Enable
  79. * ...
  80. * bit 15 / 31 => nsaid15 read/write Enable
  81. */
  82. writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
  83. /* bit 30 / 31 => Secure Global Enable : write/read */
  84. /* bit 0 / 1 => Region Enable for filter 0/1 */
  85. writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
  86. /* Enable Filter 0 and 1 */
  87. setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
  88. /* RCC trust zone deactivated */
  89. writel(0x0, RCC_TZCR);
  90. /* TAMP: deactivate the internal tamper
  91. * Bit 23 ITAMP8E: monotonic counter overflow
  92. * Bit 20 ITAMP5E: RTC calendar overflow
  93. * Bit 19 ITAMP4E: HSE monitoring
  94. * Bit 18 ITAMP3E: LSE monitoring
  95. * Bit 16 ITAMP1E: RTC power domain supply monitoring
  96. */
  97. writel(0x0, TAMP_CR1);
  98. }
  99. /*
  100. * Debug init
  101. */
  102. static void dbgmcu_init(void)
  103. {
  104. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  105. /* Freeze IWDG2 if Cortex-A7 is in debug mode */
  106. setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
  107. }
  108. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  109. static u32 get_bootmode(void)
  110. {
  111. u32 boot_mode;
  112. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  113. u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
  114. u32 bootrom_device, bootrom_instance;
  115. bootrom_device =
  116. (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
  117. bootrom_instance =
  118. (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
  119. boot_mode =
  120. ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
  121. ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
  122. BOOT_INSTANCE_MASK);
  123. /* save the boot mode in TAMP backup register */
  124. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  125. TAMP_BOOT_MODE_MASK,
  126. boot_mode << TAMP_BOOT_MODE_SHIFT);
  127. #else
  128. /* read TAMP backup register */
  129. boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
  130. TAMP_BOOT_MODE_SHIFT;
  131. #endif
  132. return boot_mode;
  133. }
  134. /*
  135. * Early system init
  136. */
  137. int arch_cpu_init(void)
  138. {
  139. u32 boot_mode;
  140. /* early armv7 timer init: needed for polling */
  141. timer_init();
  142. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  143. dbgmcu_init();
  144. security_init();
  145. #endif
  146. /* get bootmode from BootRom context: saved in TAMP register */
  147. boot_mode = get_bootmode();
  148. if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
  149. gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
  150. #if defined(CONFIG_DEBUG_UART) && \
  151. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  152. else
  153. debug_uart_init();
  154. #endif
  155. return 0;
  156. }
  157. void enable_caches(void)
  158. {
  159. /* Enable D-cache. I-cache is already enabled in start.S */
  160. dcache_enable();
  161. }
  162. static u32 read_idc(void)
  163. {
  164. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  165. return readl(DBGMCU_IDC);
  166. }
  167. u32 get_cpu_rev(void)
  168. {
  169. return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
  170. }
  171. u32 get_cpu_type(void)
  172. {
  173. return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
  174. }
  175. #if defined(CONFIG_DISPLAY_CPUINFO)
  176. int print_cpuinfo(void)
  177. {
  178. char *cpu_s, *cpu_r;
  179. switch (get_cpu_type()) {
  180. case CPU_STMP32MP15x:
  181. cpu_s = "15x";
  182. break;
  183. default:
  184. cpu_s = "?";
  185. break;
  186. }
  187. switch (get_cpu_rev()) {
  188. case CPU_REVA:
  189. cpu_r = "A";
  190. break;
  191. case CPU_REVB:
  192. cpu_r = "B";
  193. break;
  194. default:
  195. cpu_r = "?";
  196. break;
  197. }
  198. printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r);
  199. return 0;
  200. }
  201. #endif /* CONFIG_DISPLAY_CPUINFO */
  202. static void setup_boot_mode(void)
  203. {
  204. char cmd[60];
  205. u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
  206. u32 boot_mode =
  207. (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
  208. int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  209. pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n",
  210. __func__, boot_ctx, boot_mode, instance);
  211. switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
  212. case BOOT_SERIAL_UART:
  213. sprintf(cmd, "%d", instance);
  214. env_set("boot_device", "uart");
  215. env_set("boot_instance", cmd);
  216. break;
  217. case BOOT_SERIAL_USB:
  218. env_set("boot_device", "usb");
  219. env_set("boot_instance", "0");
  220. break;
  221. case BOOT_FLASH_SD:
  222. case BOOT_FLASH_EMMC:
  223. sprintf(cmd, "%d", instance);
  224. env_set("boot_device", "mmc");
  225. env_set("boot_instance", cmd);
  226. break;
  227. case BOOT_FLASH_NAND:
  228. env_set("boot_device", "nand");
  229. env_set("boot_instance", "0");
  230. break;
  231. case BOOT_FLASH_NOR:
  232. env_set("boot_device", "nor");
  233. env_set("boot_instance", "0");
  234. break;
  235. default:
  236. pr_debug("unexpected boot mode = %x\n", boot_mode);
  237. break;
  238. }
  239. }
  240. /*
  241. * If there is no MAC address in the environment, then it will be initialized
  242. * (silently) from the value in the OTP.
  243. */
  244. static int setup_mac_address(void)
  245. {
  246. #if defined(CONFIG_NET)
  247. int ret;
  248. int i;
  249. u32 otp[2];
  250. uchar enetaddr[6];
  251. struct udevice *dev;
  252. /* MAC already in environment */
  253. if (eth_env_get_enetaddr("ethaddr", enetaddr))
  254. return 0;
  255. ret = uclass_get_device_by_driver(UCLASS_MISC,
  256. DM_GET_DRIVER(stm32mp_bsec),
  257. &dev);
  258. if (ret)
  259. return ret;
  260. ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
  261. otp, sizeof(otp));
  262. if (ret < 0)
  263. return ret;
  264. for (i = 0; i < 6; i++)
  265. enetaddr[i] = ((uint8_t *)&otp)[i];
  266. if (!is_valid_ethaddr(enetaddr)) {
  267. pr_err("invalid MAC address in OTP %pM", enetaddr);
  268. return -EINVAL;
  269. }
  270. pr_debug("OTP MAC address = %pM\n", enetaddr);
  271. ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
  272. if (!ret)
  273. pr_err("Failed to set mac address %pM from OTP: %d\n",
  274. enetaddr, ret);
  275. #endif
  276. return 0;
  277. }
  278. static int setup_serial_number(void)
  279. {
  280. char serial_string[25];
  281. u32 otp[3] = {0, 0, 0 };
  282. struct udevice *dev;
  283. int ret;
  284. if (env_get("serial#"))
  285. return 0;
  286. ret = uclass_get_device_by_driver(UCLASS_MISC,
  287. DM_GET_DRIVER(stm32mp_bsec),
  288. &dev);
  289. if (ret)
  290. return ret;
  291. ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
  292. otp, sizeof(otp));
  293. if (ret < 0)
  294. return ret;
  295. sprintf(serial_string, "%08x%08x%08x", otp[0], otp[1], otp[2]);
  296. env_set("serial#", serial_string);
  297. return 0;
  298. }
  299. int arch_misc_init(void)
  300. {
  301. setup_boot_mode();
  302. setup_mac_address();
  303. setup_serial_number();
  304. return 0;
  305. }