config.h 3.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Lei Wen <leiwen@marvell.com>
  6. */
  7. /*
  8. * This file should be included in board config header file.
  9. *
  10. * It supports common definitions for Kirkwood platform
  11. */
  12. #ifndef _KW_CONFIG_H
  13. #define _KW_CONFIG_H
  14. #if defined (CONFIG_KW88F6281)
  15. #include <asm/arch/kw88f6281.h>
  16. #elif defined (CONFIG_KW88F6192)
  17. #include <asm/arch/kw88f6192.h>
  18. #else
  19. #error "SOC Name not defined"
  20. #endif /* CONFIG_KW88F6281 */
  21. #include <asm/arch/soc.h>
  22. #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
  23. #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
  24. #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
  25. /*
  26. * By default kwbimage.cfg from board specific folder is used
  27. * If for some board, different configuration file need to be used,
  28. * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
  29. */
  30. #ifndef CONFIG_SYS_KWD_CONFIG
  31. #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
  32. #endif /* CONFIG_SYS_KWD_CONFIG */
  33. /* Kirkwood has 2k of Security SRAM, use it for SP */
  34. #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
  35. #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
  36. #define MV_UART_CONSOLE_BASE KW_UART0_BASE
  37. #define MV_SATA_BASE KW_SATA_BASE
  38. #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
  39. #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
  40. /*
  41. * NAND configuration
  42. */
  43. #ifdef CONFIG_CMD_NAND
  44. #define CONFIG_NAND_KIRKWOOD
  45. #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
  46. #define NAND_ALLOW_ERASE_ALL 1
  47. #endif
  48. /*
  49. * SPI Flash configuration
  50. */
  51. #ifdef CONFIG_CMD_SF
  52. #ifndef CONFIG_ENV_SPI_BUS
  53. # define CONFIG_ENV_SPI_BUS 0
  54. #endif
  55. #ifndef CONFIG_ENV_SPI_CS
  56. # define CONFIG_ENV_SPI_CS 0
  57. #endif
  58. #ifndef CONFIG_ENV_SPI_MAX_HZ
  59. # define CONFIG_ENV_SPI_MAX_HZ 50000000
  60. #endif
  61. #endif
  62. /*
  63. * Ethernet Driver configuration
  64. */
  65. #ifdef CONFIG_CMD_NET
  66. #define CONFIG_NETCONSOLE /* include NetConsole support */
  67. #define CONFIG_MII /* expose smi ove miiphy interface */
  68. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
  69. #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
  70. #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
  71. #endif /* CONFIG_CMD_NET */
  72. /*
  73. * USB/EHCI
  74. */
  75. #ifdef CONFIG_CMD_USB
  76. #define CONFIG_EHCI_IS_TDI
  77. #endif /* CONFIG_CMD_USB */
  78. /*
  79. * IDE Support on SATA ports
  80. */
  81. #ifdef CONFIG_IDE
  82. #define __io
  83. #define CONFIG_IDE_PREINIT
  84. #define CONFIG_MVSATA_IDE_USE_PORT1
  85. /* Needs byte-swapping for ATA data register */
  86. #define CONFIG_IDE_SWAP_IO
  87. /* Data, registers and alternate blocks are at the same offset */
  88. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
  89. #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
  90. #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
  91. /* Each 8-bit ATA register is aligned to a 4-bytes address */
  92. #define CONFIG_SYS_ATA_STRIDE 4
  93. /* Controller supports 48-bits LBA addressing */
  94. #define CONFIG_LBA48
  95. /* CONFIG_IDE requires some #defines for ATA registers */
  96. #define CONFIG_SYS_IDE_MAXBUS 2
  97. #define CONFIG_SYS_IDE_MAXDEVICE 2
  98. /* ATA registers base is at SATA controller base */
  99. #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
  100. #endif /* CONFIG_IDE */
  101. /*
  102. * I2C related stuff
  103. */
  104. #if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
  105. #ifndef CONFIG_SYS_I2C_SOFT
  106. #define CONFIG_SYS_I2C
  107. #define CONFIG_SYS_I2C_MVTWSI
  108. #endif
  109. #define CONFIG_SYS_I2C_SLAVE 0x0
  110. #define CONFIG_SYS_I2C_SPEED 100000
  111. #endif
  112. /* Use common timer */
  113. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  114. #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
  115. #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
  116. #endif /* _KW_CONFIG_H */