uniphier-system-bus.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include <linux/bitops.h>
  3. #include <linux/errno.h>
  4. #include <linux/io.h>
  5. #include <linux/sizes.h>
  6. #include <linux/types.h>
  7. #include <dm.h>
  8. /* System Bus Controller registers */
  9. #define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
  10. #define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */
  11. #define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
  12. #define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
  13. #define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
  14. #define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
  15. #define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
  16. #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
  17. #if 1
  18. /* slower but LED works */
  19. #define SBCTRL0_VALUE 0x55450000
  20. #define SBCTRL1_VALUE 0x07168d00
  21. #define SBCTRL2_VALUE 0x34000009
  22. #define SBCTRL4_VALUE 0x02110110
  23. #else
  24. /* faster but LED does not work */
  25. #define SBCTRL0_VALUE 0x55450000
  26. #define SBCTRL1_VALUE 0x06057700
  27. /* NOR flash needs more wait counts than SRAM */
  28. #define SBCTRL2_VALUE 0x34000009
  29. #define SBCTRL4_VALUE 0x02110210
  30. #endif
  31. void uniphier_system_bus_set_reg(void __iomem *membase)
  32. {
  33. void __iomem *bank0_base = membase;
  34. void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE;
  35. /*
  36. * Only CS1 is connected to support card.
  37. * BKSZ[1:0] should be set to "01".
  38. */
  39. writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0);
  40. writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1);
  41. writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2);
  42. writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4);
  43. if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) {
  44. /*
  45. * Boot Swap On: boot from external NOR/SRAM
  46. * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  47. *
  48. * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  49. * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  50. */
  51. writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE);
  52. } else {
  53. /*
  54. * Boot Swap Off: boot from mask ROM
  55. * 0x40000000-0x41ffffff: mask ROM
  56. * 0x42000000-0x43efffff: memory bank (31MB)
  57. * 0x43f00000-0x43ffffff: peripherals (1MB)
  58. */
  59. writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */
  60. writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE);
  61. }
  62. }
  63. static int uniphier_system_bus_probe(struct udevice *dev)
  64. {
  65. fdt_addr_t base;
  66. void __iomem *membase;
  67. base = dev_read_addr(dev);
  68. if (base == FDT_ADDR_T_NONE)
  69. return -EINVAL;
  70. membase = devm_ioremap(dev, base, SZ_1K);
  71. if (!membase)
  72. return -ENOMEM;
  73. uniphier_system_bus_set_reg(membase);
  74. return 0;
  75. }
  76. static const struct udevice_id uniphier_system_bus_match[] = {
  77. { .compatible = "socionext,uniphier-system-bus" },
  78. { /* sentinel */ }
  79. };
  80. U_BOOT_DRIVER(uniphier_system_bus_driver) = {
  81. .name = "uniphier-system-bus",
  82. .id = UCLASS_SIMPLE_BUS,
  83. .of_match = uniphier_system_bus_match,
  84. .probe = uniphier_system_bus_probe,
  85. };