zynq_spi.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq PS SPI controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <time.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
  19. #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  20. #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  21. #define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
  22. #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  23. #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  24. #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  25. #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  26. #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  27. #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  28. #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  29. #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  30. #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  31. #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  32. #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
  33. #define ZYNQ_SPI_FIFO_DEPTH 128
  34. #define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
  35. /* zynq spi register set */
  36. struct zynq_spi_regs {
  37. u32 cr; /* 0x00 */
  38. u32 isr; /* 0x04 */
  39. u32 ier; /* 0x08 */
  40. u32 idr; /* 0x0C */
  41. u32 imr; /* 0x10 */
  42. u32 enr; /* 0x14 */
  43. u32 dr; /* 0x18 */
  44. u32 txdr; /* 0x1C */
  45. u32 rxdr; /* 0x20 */
  46. };
  47. /* zynq spi platform data */
  48. struct zynq_spi_platdata {
  49. struct zynq_spi_regs *regs;
  50. u32 frequency; /* input frequency */
  51. u32 speed_hz;
  52. uint deactivate_delay_us; /* Delay to wait after deactivate */
  53. uint activate_delay_us; /* Delay to wait after activate */
  54. };
  55. /* zynq spi priv */
  56. struct zynq_spi_priv {
  57. struct zynq_spi_regs *regs;
  58. u8 cs;
  59. u8 mode;
  60. ulong last_transaction_us; /* Time of last transaction end */
  61. u8 fifo_depth;
  62. u32 freq; /* required frequency */
  63. };
  64. static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
  65. {
  66. struct zynq_spi_platdata *plat = bus->platdata;
  67. const void *blob = gd->fdt_blob;
  68. int node = dev_of_offset(bus);
  69. plat->regs = dev_read_addr_ptr(bus);
  70. /* FIXME: Use 250MHz as a suitable default */
  71. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  72. 250000000);
  73. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  74. "spi-deactivate-delay", 0);
  75. plat->activate_delay_us = fdtdec_get_int(blob, node,
  76. "spi-activate-delay", 0);
  77. plat->speed_hz = plat->frequency / 2;
  78. debug("%s: regs=%p max-frequency=%d\n", __func__,
  79. plat->regs, plat->frequency);
  80. return 0;
  81. }
  82. static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
  83. {
  84. struct zynq_spi_regs *regs = priv->regs;
  85. u32 confr;
  86. /* Disable SPI */
  87. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  88. writel(~confr, &regs->enr);
  89. /* Disable Interrupts */
  90. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
  91. /* Clear RX FIFO */
  92. while (readl(&regs->isr) &
  93. ZYNQ_SPI_IXR_RXNEMPTY_MASK)
  94. readl(&regs->rxdr);
  95. /* Clear Interrupts */
  96. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
  97. /* Manual slave select and Auto start */
  98. confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
  99. ZYNQ_SPI_CR_MSTREN_MASK;
  100. confr &= ~ZYNQ_SPI_CR_MSA_MASK;
  101. writel(confr, &regs->cr);
  102. /* Enable SPI */
  103. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  104. }
  105. static int zynq_spi_probe(struct udevice *bus)
  106. {
  107. struct zynq_spi_platdata *plat = dev_get_platdata(bus);
  108. struct zynq_spi_priv *priv = dev_get_priv(bus);
  109. priv->regs = plat->regs;
  110. priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
  111. /* init the zynq spi hw */
  112. zynq_spi_init_hw(priv);
  113. return 0;
  114. }
  115. static void spi_cs_activate(struct udevice *dev)
  116. {
  117. struct udevice *bus = dev->parent;
  118. struct zynq_spi_platdata *plat = bus->platdata;
  119. struct zynq_spi_priv *priv = dev_get_priv(bus);
  120. struct zynq_spi_regs *regs = priv->regs;
  121. u32 cr;
  122. /* If it's too soon to do another transaction, wait */
  123. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  124. ulong delay_us; /* The delay completed so far */
  125. delay_us = timer_get_us() - priv->last_transaction_us;
  126. if (delay_us < plat->deactivate_delay_us)
  127. udelay(plat->deactivate_delay_us - delay_us);
  128. }
  129. clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  130. cr = readl(&regs->cr);
  131. /*
  132. * CS cal logic: CS[13:10]
  133. * xxx0 - cs0
  134. * xx01 - cs1
  135. * x011 - cs2
  136. */
  137. cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
  138. writel(cr, &regs->cr);
  139. if (plat->activate_delay_us)
  140. udelay(plat->activate_delay_us);
  141. }
  142. static void spi_cs_deactivate(struct udevice *dev)
  143. {
  144. struct udevice *bus = dev->parent;
  145. struct zynq_spi_platdata *plat = bus->platdata;
  146. struct zynq_spi_priv *priv = dev_get_priv(bus);
  147. struct zynq_spi_regs *regs = priv->regs;
  148. setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  149. /* Remember time of this transaction so we can honour the bus delay */
  150. if (plat->deactivate_delay_us)
  151. priv->last_transaction_us = timer_get_us();
  152. }
  153. static int zynq_spi_claim_bus(struct udevice *dev)
  154. {
  155. struct udevice *bus = dev->parent;
  156. struct zynq_spi_priv *priv = dev_get_priv(bus);
  157. struct zynq_spi_regs *regs = priv->regs;
  158. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  159. return 0;
  160. }
  161. static int zynq_spi_release_bus(struct udevice *dev)
  162. {
  163. struct udevice *bus = dev->parent;
  164. struct zynq_spi_priv *priv = dev_get_priv(bus);
  165. struct zynq_spi_regs *regs = priv->regs;
  166. u32 confr;
  167. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  168. writel(~confr, &regs->enr);
  169. return 0;
  170. }
  171. static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
  172. const void *dout, void *din, unsigned long flags)
  173. {
  174. struct udevice *bus = dev->parent;
  175. struct zynq_spi_priv *priv = dev_get_priv(bus);
  176. struct zynq_spi_regs *regs = priv->regs;
  177. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  178. u32 len = bitlen / 8;
  179. u32 tx_len = len, rx_len = len, tx_tvl;
  180. const u8 *tx_buf = dout;
  181. u8 *rx_buf = din, buf;
  182. u32 ts, status;
  183. debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  184. bus->seq, slave_plat->cs, bitlen, len, flags);
  185. if (bitlen % 8) {
  186. debug("spi_xfer: Non byte aligned SPI transfer\n");
  187. return -1;
  188. }
  189. priv->cs = slave_plat->cs;
  190. if (flags & SPI_XFER_BEGIN)
  191. spi_cs_activate(dev);
  192. while (rx_len > 0) {
  193. /* Write the data into TX FIFO - tx threshold is fifo_depth */
  194. tx_tvl = 0;
  195. while ((tx_tvl < priv->fifo_depth) && tx_len) {
  196. if (tx_buf)
  197. buf = *tx_buf++;
  198. else
  199. buf = 0;
  200. writel(buf, &regs->txdr);
  201. tx_len--;
  202. tx_tvl++;
  203. }
  204. /* Check TX FIFO completion */
  205. ts = get_timer(0);
  206. status = readl(&regs->isr);
  207. while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
  208. if (get_timer(ts) > ZYNQ_SPI_WAIT) {
  209. printf("spi_xfer: Timeout! TX FIFO not full\n");
  210. return -1;
  211. }
  212. status = readl(&regs->isr);
  213. }
  214. /* Read the data from RX FIFO */
  215. status = readl(&regs->isr);
  216. while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
  217. buf = readl(&regs->rxdr);
  218. if (rx_buf)
  219. *rx_buf++ = buf;
  220. status = readl(&regs->isr);
  221. rx_len--;
  222. }
  223. }
  224. if (flags & SPI_XFER_END)
  225. spi_cs_deactivate(dev);
  226. return 0;
  227. }
  228. static int zynq_spi_set_speed(struct udevice *bus, uint speed)
  229. {
  230. struct zynq_spi_platdata *plat = bus->platdata;
  231. struct zynq_spi_priv *priv = dev_get_priv(bus);
  232. struct zynq_spi_regs *regs = priv->regs;
  233. uint32_t confr;
  234. u8 baud_rate_val = 0;
  235. if (speed > plat->frequency)
  236. speed = plat->frequency;
  237. /* Set the clock frequency */
  238. confr = readl(&regs->cr);
  239. if (speed == 0) {
  240. /* Set baudrate x8, if the freq is 0 */
  241. baud_rate_val = 0x2;
  242. } else if (plat->speed_hz != speed) {
  243. while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
  244. ((plat->frequency /
  245. (2 << baud_rate_val)) > speed))
  246. baud_rate_val++;
  247. plat->speed_hz = speed / (2 << baud_rate_val);
  248. }
  249. confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
  250. confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
  251. writel(confr, &regs->cr);
  252. priv->freq = speed;
  253. debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
  254. priv->regs, priv->freq);
  255. return 0;
  256. }
  257. static int zynq_spi_set_mode(struct udevice *bus, uint mode)
  258. {
  259. struct zynq_spi_priv *priv = dev_get_priv(bus);
  260. struct zynq_spi_regs *regs = priv->regs;
  261. uint32_t confr;
  262. /* Set the SPI Clock phase and polarities */
  263. confr = readl(&regs->cr);
  264. confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
  265. if (mode & SPI_CPHA)
  266. confr |= ZYNQ_SPI_CR_CPHA_MASK;
  267. if (mode & SPI_CPOL)
  268. confr |= ZYNQ_SPI_CR_CPOL_MASK;
  269. writel(confr, &regs->cr);
  270. priv->mode = mode;
  271. debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
  272. return 0;
  273. }
  274. static const struct dm_spi_ops zynq_spi_ops = {
  275. .claim_bus = zynq_spi_claim_bus,
  276. .release_bus = zynq_spi_release_bus,
  277. .xfer = zynq_spi_xfer,
  278. .set_speed = zynq_spi_set_speed,
  279. .set_mode = zynq_spi_set_mode,
  280. };
  281. static const struct udevice_id zynq_spi_ids[] = {
  282. { .compatible = "xlnx,zynq-spi-r1p6" },
  283. { .compatible = "cdns,spi-r1p6" },
  284. { }
  285. };
  286. U_BOOT_DRIVER(zynq_spi) = {
  287. .name = "zynq_spi",
  288. .id = UCLASS_SPI,
  289. .of_match = zynq_spi_ids,
  290. .ops = &zynq_spi_ops,
  291. .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
  292. .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
  293. .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
  294. .probe = zynq_spi_probe,
  295. };