mtk_snfi_spi.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <spi.h>
  12. #include <spi-mem.h>
  13. #include <stdbool.h>
  14. #include <watchdog.h>
  15. #include <dm/pinctrl.h>
  16. #include <linux/bitops.h>
  17. #include <linux/io.h>
  18. #include <linux/iopoll.h>
  19. #define SNFI_MAC_CTL 0x500
  20. #define MAC_XIO_SEL BIT(4)
  21. #define SF_MAC_EN BIT(3)
  22. #define SF_TRIG BIT(2)
  23. #define WIP_READY BIT(1)
  24. #define WIP BIT(0)
  25. #define SNFI_MAC_OUTL 0x504
  26. #define SNFI_MAC_INL 0x508
  27. #define SNFI_MISC_CTL 0x538
  28. #define SW_RST BIT(28)
  29. #define FIFO_RD_LTC_SHIFT 25
  30. #define FIFO_RD_LTC GENMASK(26, 25)
  31. #define LATCH_LAT_SHIFT 8
  32. #define LATCH_LAT GENMASK(9, 8)
  33. #define CS_DESELECT_CYC_SHIFT 0
  34. #define CS_DESELECT_CYC GENMASK(4, 0)
  35. #define SNF_STA_CTL1 0x550
  36. #define SPI_STATE GENMASK(3, 0)
  37. #define SNFI_GPRAM_OFFSET 0x800
  38. #define SNFI_GPRAM_SIZE 0x80
  39. #define SNFI_POLL_INTERVAL 500000
  40. #define SNFI_RST_POLL_INTERVAL 1000000
  41. struct mtk_snfi_priv {
  42. void __iomem *base;
  43. struct clk nfi_clk;
  44. struct clk pad_clk;
  45. };
  46. static int mtk_snfi_adjust_op_size(struct spi_slave *slave,
  47. struct spi_mem_op *op)
  48. {
  49. u32 nbytes;
  50. /*
  51. * When there is input data, it will be appended after the output
  52. * data in the GPRAM. So the total size of either pure output data
  53. * or the output+input data must not exceed the GPRAM size.
  54. */
  55. nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes +
  56. op->dummy.nbytes;
  57. if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE)
  58. return 0;
  59. if (nbytes >= SNFI_GPRAM_SIZE)
  60. return -ENOTSUPP;
  61. op->data.nbytes = SNFI_GPRAM_SIZE - nbytes;
  62. return 0;
  63. }
  64. static bool mtk_snfi_supports_op(struct spi_slave *slave,
  65. const struct spi_mem_op *op)
  66. {
  67. if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
  68. op->dummy.buswidth > 1 || op->data.buswidth > 1)
  69. return false;
  70. return true;
  71. }
  72. static int mtk_snfi_mac_trigger(struct mtk_snfi_priv *priv,
  73. struct udevice *bus, u32 outlen, u32 inlen)
  74. {
  75. int ret;
  76. u32 val;
  77. #ifdef CONFIG_PINCTRL
  78. pinctrl_select_state(bus, "snfi");
  79. #endif
  80. writel(SF_MAC_EN, priv->base + SNFI_MAC_CTL);
  81. writel(outlen, priv->base + SNFI_MAC_OUTL);
  82. writel(inlen, priv->base + SNFI_MAC_INL);
  83. writel(SF_MAC_EN | SF_TRIG, priv->base + SNFI_MAC_CTL);
  84. ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val,
  85. val & WIP_READY, SNFI_POLL_INTERVAL);
  86. if (ret) {
  87. printf("%s: timed out waiting for WIP_READY\n", __func__);
  88. goto cleanup;
  89. }
  90. ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val,
  91. !(val & WIP), SNFI_POLL_INTERVAL);
  92. if (ret)
  93. printf("%s: timed out waiting for WIP cleared\n", __func__);
  94. writel(0, priv->base + SNFI_MAC_CTL);
  95. cleanup:
  96. #ifdef CONFIG_PINCTRL
  97. pinctrl_select_state(bus, "default");
  98. #endif
  99. return ret;
  100. }
  101. static int mtk_snfi_mac_reset(struct mtk_snfi_priv *priv)
  102. {
  103. int ret;
  104. u32 val;
  105. setbits_32(priv->base + SNFI_MISC_CTL, SW_RST);
  106. ret = readl_poll_timeout(priv->base + SNF_STA_CTL1, val,
  107. !(val & SPI_STATE), SNFI_POLL_INTERVAL);
  108. if (ret)
  109. printf("%s: failed to reset snfi mac\n", __func__);
  110. writel((2 << FIFO_RD_LTC_SHIFT) |
  111. (10 << CS_DESELECT_CYC_SHIFT),
  112. priv->base + SNFI_MISC_CTL);
  113. return ret;
  114. }
  115. static void mtk_snfi_copy_to_gpram(struct mtk_snfi_priv *priv,
  116. const void *data, size_t len)
  117. {
  118. void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET;
  119. size_t i, n = (len + sizeof(u32) - 1) / sizeof(u32);
  120. const u32 *buff = data;
  121. /*
  122. * The output data will always be copied to the beginning of
  123. * the GPRAM. Uses word write for better performace.
  124. *
  125. * Trailing bytes in the last word are not cared.
  126. */
  127. for (i = 0; i < n; i++)
  128. writel(buff[i], gpram + i * sizeof(u32));
  129. }
  130. static void mtk_snfi_copy_from_gpram(struct mtk_snfi_priv *priv, u8 *cache,
  131. void *data, size_t pos, size_t len)
  132. {
  133. void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET;
  134. u32 *buff = (u32 *)cache;
  135. size_t i, off, end;
  136. /* Start position in the buffer */
  137. off = pos & (sizeof(u32) - 1);
  138. /* End position for copy */
  139. end = (len + pos + sizeof(u32) - 1) & (~(sizeof(u32) - 1));
  140. /* Start position for copy */
  141. pos &= ~(sizeof(u32) - 1);
  142. /*
  143. * Read aligned data from GPRAM to buffer first.
  144. * Uses word read for better performace.
  145. */
  146. i = 0;
  147. while (pos < end) {
  148. buff[i++] = readl(gpram + pos);
  149. pos += sizeof(u32);
  150. }
  151. /* Copy rx data */
  152. memcpy(data, cache + off, len);
  153. }
  154. static int mtk_snfi_exec_op(struct spi_slave *slave,
  155. const struct spi_mem_op *op)
  156. {
  157. struct udevice *bus = dev_get_parent(slave->dev);
  158. struct mtk_snfi_priv *priv = dev_get_priv(bus);
  159. u8 gpram_cache[SNFI_GPRAM_SIZE];
  160. u32 i, len = 0, inlen = 0;
  161. int addr_sh;
  162. int ret;
  163. WATCHDOG_RESET();
  164. ret = mtk_snfi_mac_reset(priv);
  165. if (ret)
  166. return ret;
  167. /* Put opcode */
  168. gpram_cache[len++] = op->cmd.opcode;
  169. /* Put address */
  170. addr_sh = (op->addr.nbytes - 1) * 8;
  171. while (addr_sh >= 0) {
  172. gpram_cache[len++] = (op->addr.val >> addr_sh) & 0xff;
  173. addr_sh -= 8;
  174. }
  175. /* Put dummy bytes */
  176. for (i = 0; i < op->dummy.nbytes; i++)
  177. gpram_cache[len++] = 0;
  178. /* Put output data */
  179. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) {
  180. memcpy(gpram_cache + len, op->data.buf.out, op->data.nbytes);
  181. len += op->data.nbytes;
  182. }
  183. /* Copy final output data to GPRAM */
  184. mtk_snfi_copy_to_gpram(priv, gpram_cache, len);
  185. /* Start one SPI transaction */
  186. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  187. inlen = op->data.nbytes;
  188. ret = mtk_snfi_mac_trigger(priv, bus, len, inlen);
  189. if (ret)
  190. return ret;
  191. /* Copy input data from GPRAM */
  192. if (inlen)
  193. mtk_snfi_copy_from_gpram(priv, gpram_cache, op->data.buf.in,
  194. len, inlen);
  195. return 0;
  196. }
  197. static int mtk_snfi_spi_probe(struct udevice *bus)
  198. {
  199. struct mtk_snfi_priv *priv = dev_get_priv(bus);
  200. int ret;
  201. priv->base = dev_read_addr_ptr(bus);
  202. if (!priv->base)
  203. return -EINVAL;
  204. ret = clk_get_by_name(bus, "nfi_clk", &priv->nfi_clk);
  205. if (ret < 0)
  206. return ret;
  207. ret = clk_get_by_name(bus, "pad_clk", &priv->pad_clk);
  208. if (ret < 0)
  209. return ret;
  210. clk_enable(&priv->nfi_clk);
  211. clk_enable(&priv->pad_clk);
  212. return 0;
  213. }
  214. static int mtk_snfi_set_speed(struct udevice *bus, uint speed)
  215. {
  216. /*
  217. * The SNFI does not have a bus clock divider.
  218. * The bus clock is set in dts (pad_clk, UNIVPLL2_D8 = 50MHz).
  219. */
  220. return 0;
  221. }
  222. static int mtk_snfi_set_mode(struct udevice *bus, uint mode)
  223. {
  224. /* The SNFI supports only mode 0 */
  225. if (mode)
  226. return -EINVAL;
  227. return 0;
  228. }
  229. static const struct spi_controller_mem_ops mtk_snfi_mem_ops = {
  230. .adjust_op_size = mtk_snfi_adjust_op_size,
  231. .supports_op = mtk_snfi_supports_op,
  232. .exec_op = mtk_snfi_exec_op,
  233. };
  234. static const struct dm_spi_ops mtk_snfi_spi_ops = {
  235. .mem_ops = &mtk_snfi_mem_ops,
  236. .set_speed = mtk_snfi_set_speed,
  237. .set_mode = mtk_snfi_set_mode,
  238. };
  239. static const struct udevice_id mtk_snfi_spi_ids[] = {
  240. { .compatible = "mediatek,mtk-snfi-spi" },
  241. { }
  242. };
  243. U_BOOT_DRIVER(mtk_snfi_spi) = {
  244. .name = "mtk_snfi_spi",
  245. .id = UCLASS_SPI,
  246. .of_match = mtk_snfi_spi_ids,
  247. .ops = &mtk_snfi_spi_ops,
  248. .priv_auto_alloc_size = sizeof(struct mtk_snfi_priv),
  249. .probe = mtk_snfi_spi_probe,
  250. };