designware_spi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Designware master SPI core controller driver
  4. *
  5. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  6. *
  7. * Very loosely based on the Linux driver:
  8. * drivers/spi/spi-dw.c, which is:
  9. * Copyright (c) 2009, Intel Corporation.
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <asm-generic/gpio.h>
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <errno.h>
  17. #include <malloc.h>
  18. #include <spi.h>
  19. #include <fdtdec.h>
  20. #include <reset.h>
  21. #include <dm/device_compat.h>
  22. #include <linux/bitops.h>
  23. #include <linux/compat.h>
  24. #include <linux/iopoll.h>
  25. #include <asm/io.h>
  26. /* Register offsets */
  27. #define DW_SPI_CTRL0 0x00
  28. #define DW_SPI_CTRL1 0x04
  29. #define DW_SPI_SSIENR 0x08
  30. #define DW_SPI_MWCR 0x0c
  31. #define DW_SPI_SER 0x10
  32. #define DW_SPI_BAUDR 0x14
  33. #define DW_SPI_TXFLTR 0x18
  34. #define DW_SPI_RXFLTR 0x1c
  35. #define DW_SPI_TXFLR 0x20
  36. #define DW_SPI_RXFLR 0x24
  37. #define DW_SPI_SR 0x28
  38. #define DW_SPI_IMR 0x2c
  39. #define DW_SPI_ISR 0x30
  40. #define DW_SPI_RISR 0x34
  41. #define DW_SPI_TXOICR 0x38
  42. #define DW_SPI_RXOICR 0x3c
  43. #define DW_SPI_RXUICR 0x40
  44. #define DW_SPI_MSTICR 0x44
  45. #define DW_SPI_ICR 0x48
  46. #define DW_SPI_DMACR 0x4c
  47. #define DW_SPI_DMATDLR 0x50
  48. #define DW_SPI_DMARDLR 0x54
  49. #define DW_SPI_IDR 0x58
  50. #define DW_SPI_VERSION 0x5c
  51. #define DW_SPI_DR 0x60
  52. /* Bit fields in CTRLR0 */
  53. #define SPI_DFS_OFFSET 0
  54. #define SPI_FRF_OFFSET 4
  55. #define SPI_FRF_SPI 0x0
  56. #define SPI_FRF_SSP 0x1
  57. #define SPI_FRF_MICROWIRE 0x2
  58. #define SPI_FRF_RESV 0x3
  59. #define SPI_MODE_OFFSET 6
  60. #define SPI_SCPH_OFFSET 6
  61. #define SPI_SCOL_OFFSET 7
  62. #define SPI_TMOD_OFFSET 8
  63. #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
  64. #define SPI_TMOD_TR 0x0 /* xmit & recv */
  65. #define SPI_TMOD_TO 0x1 /* xmit only */
  66. #define SPI_TMOD_RO 0x2 /* recv only */
  67. #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
  68. #define SPI_SLVOE_OFFSET 10
  69. #define SPI_SRL_OFFSET 11
  70. #define SPI_CFS_OFFSET 12
  71. /* Bit fields in SR, 7 bits */
  72. #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
  73. #define SR_BUSY BIT(0)
  74. #define SR_TF_NOT_FULL BIT(1)
  75. #define SR_TF_EMPT BIT(2)
  76. #define SR_RF_NOT_EMPT BIT(3)
  77. #define SR_RF_FULL BIT(4)
  78. #define SR_TX_ERR BIT(5)
  79. #define SR_DCOL BIT(6)
  80. #define RX_TIMEOUT 1000 /* timeout in ms */
  81. struct dw_spi_platdata {
  82. s32 frequency; /* Default clock frequency, -1 for none */
  83. void __iomem *regs;
  84. };
  85. struct dw_spi_priv {
  86. void __iomem *regs;
  87. unsigned int freq; /* Default frequency */
  88. unsigned int mode;
  89. struct clk clk;
  90. unsigned long bus_clk_rate;
  91. struct gpio_desc cs_gpio; /* External chip-select gpio */
  92. int bits_per_word;
  93. u8 cs; /* chip select pin */
  94. u8 tmode; /* TR/TO/RO/EEPROM */
  95. u8 type; /* SPI/SSP/MicroWire */
  96. int len;
  97. u32 fifo_len; /* depth of the FIFO buffer */
  98. void *tx;
  99. void *tx_end;
  100. void *rx;
  101. void *rx_end;
  102. struct reset_ctl_bulk resets;
  103. };
  104. static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
  105. {
  106. return __raw_readl(priv->regs + offset);
  107. }
  108. static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
  109. {
  110. __raw_writel(val, priv->regs + offset);
  111. }
  112. static int request_gpio_cs(struct udevice *bus)
  113. {
  114. #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
  115. struct dw_spi_priv *priv = dev_get_priv(bus);
  116. int ret;
  117. /* External chip select gpio line is optional */
  118. ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
  119. if (ret == -ENOENT)
  120. return 0;
  121. if (ret < 0) {
  122. printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
  123. return ret;
  124. }
  125. if (dm_gpio_is_valid(&priv->cs_gpio)) {
  126. dm_gpio_set_dir_flags(&priv->cs_gpio,
  127. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  128. }
  129. debug("%s: used external gpio for CS management\n", __func__);
  130. #endif
  131. return 0;
  132. }
  133. static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  134. {
  135. struct dw_spi_platdata *plat = bus->platdata;
  136. plat->regs = dev_read_addr_ptr(bus);
  137. /* Use 500KHz as a suitable default */
  138. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  139. 500000);
  140. debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
  141. plat->frequency);
  142. return request_gpio_cs(bus);
  143. }
  144. static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
  145. {
  146. dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
  147. }
  148. /* Restart the controller, disable all interrupts, clean rx fifo */
  149. static void spi_hw_init(struct dw_spi_priv *priv)
  150. {
  151. spi_enable_chip(priv, 0);
  152. dw_write(priv, DW_SPI_IMR, 0xff);
  153. spi_enable_chip(priv, 1);
  154. /*
  155. * Try to detect the FIFO depth if not set by interface driver,
  156. * the depth could be from 2 to 256 from HW spec
  157. */
  158. if (!priv->fifo_len) {
  159. u32 fifo;
  160. for (fifo = 1; fifo < 256; fifo++) {
  161. dw_write(priv, DW_SPI_TXFLTR, fifo);
  162. if (fifo != dw_read(priv, DW_SPI_TXFLTR))
  163. break;
  164. }
  165. priv->fifo_len = (fifo == 1) ? 0 : fifo;
  166. dw_write(priv, DW_SPI_TXFLTR, 0);
  167. }
  168. debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
  169. }
  170. /*
  171. * We define dw_spi_get_clk function as 'weak' as some targets
  172. * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
  173. * and implement dw_spi_get_clk their own way in their clock manager.
  174. */
  175. __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
  176. {
  177. struct dw_spi_priv *priv = dev_get_priv(bus);
  178. int ret;
  179. ret = clk_get_by_index(bus, 0, &priv->clk);
  180. if (ret)
  181. return ret;
  182. ret = clk_enable(&priv->clk);
  183. if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
  184. return ret;
  185. *rate = clk_get_rate(&priv->clk);
  186. if (!*rate)
  187. goto err_rate;
  188. debug("%s: get spi controller clk via device tree: %lu Hz\n",
  189. __func__, *rate);
  190. return 0;
  191. err_rate:
  192. clk_disable(&priv->clk);
  193. clk_free(&priv->clk);
  194. return -EINVAL;
  195. }
  196. static int dw_spi_reset(struct udevice *bus)
  197. {
  198. int ret;
  199. struct dw_spi_priv *priv = dev_get_priv(bus);
  200. ret = reset_get_bulk(bus, &priv->resets);
  201. if (ret) {
  202. /*
  203. * Return 0 if error due to !CONFIG_DM_RESET and reset
  204. * DT property is not present.
  205. */
  206. if (ret == -ENOENT || ret == -ENOTSUPP)
  207. return 0;
  208. dev_warn(bus, "Can't get reset: %d\n", ret);
  209. return ret;
  210. }
  211. ret = reset_deassert_bulk(&priv->resets);
  212. if (ret) {
  213. reset_release_bulk(&priv->resets);
  214. dev_err(bus, "Failed to reset: %d\n", ret);
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. static int dw_spi_probe(struct udevice *bus)
  220. {
  221. struct dw_spi_platdata *plat = dev_get_platdata(bus);
  222. struct dw_spi_priv *priv = dev_get_priv(bus);
  223. int ret;
  224. priv->regs = plat->regs;
  225. priv->freq = plat->frequency;
  226. ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
  227. if (ret)
  228. return ret;
  229. ret = dw_spi_reset(bus);
  230. if (ret)
  231. return ret;
  232. /* Currently only bits_per_word == 8 supported */
  233. priv->bits_per_word = 8;
  234. priv->tmode = 0; /* Tx & Rx */
  235. /* Basic HW init */
  236. spi_hw_init(priv);
  237. return 0;
  238. }
  239. /* Return the max entries we can fill into tx fifo */
  240. static inline u32 tx_max(struct dw_spi_priv *priv)
  241. {
  242. u32 tx_left, tx_room, rxtx_gap;
  243. tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
  244. tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
  245. /*
  246. * Another concern is about the tx/rx mismatch, we
  247. * thought about using (priv->fifo_len - rxflr - txflr) as
  248. * one maximum value for tx, but it doesn't cover the
  249. * data which is out of tx/rx fifo and inside the
  250. * shift registers. So a control from sw point of
  251. * view is taken.
  252. */
  253. rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
  254. (priv->bits_per_word >> 3);
  255. return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
  256. }
  257. /* Return the max entries we should read out of rx fifo */
  258. static inline u32 rx_max(struct dw_spi_priv *priv)
  259. {
  260. u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
  261. return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
  262. }
  263. static void dw_writer(struct dw_spi_priv *priv)
  264. {
  265. u32 max = tx_max(priv);
  266. u16 txw = 0;
  267. while (max--) {
  268. /* Set the tx word if the transfer's original "tx" is not null */
  269. if (priv->tx_end - priv->len) {
  270. if (priv->bits_per_word == 8)
  271. txw = *(u8 *)(priv->tx);
  272. else
  273. txw = *(u16 *)(priv->tx);
  274. }
  275. dw_write(priv, DW_SPI_DR, txw);
  276. debug("%s: tx=0x%02x\n", __func__, txw);
  277. priv->tx += priv->bits_per_word >> 3;
  278. }
  279. }
  280. static void dw_reader(struct dw_spi_priv *priv)
  281. {
  282. u32 max = rx_max(priv);
  283. u16 rxw;
  284. while (max--) {
  285. rxw = dw_read(priv, DW_SPI_DR);
  286. debug("%s: rx=0x%02x\n", __func__, rxw);
  287. /* Care about rx if the transfer's original "rx" is not null */
  288. if (priv->rx_end - priv->len) {
  289. if (priv->bits_per_word == 8)
  290. *(u8 *)(priv->rx) = rxw;
  291. else
  292. *(u16 *)(priv->rx) = rxw;
  293. }
  294. priv->rx += priv->bits_per_word >> 3;
  295. }
  296. }
  297. static int poll_transfer(struct dw_spi_priv *priv)
  298. {
  299. do {
  300. dw_writer(priv);
  301. dw_reader(priv);
  302. } while (priv->rx_end > priv->rx);
  303. return 0;
  304. }
  305. /*
  306. * We define external_cs_manage function as 'weak' as some targets
  307. * (like MSCC Ocelot) don't control the external CS pin using a GPIO
  308. * controller. These SoCs use specific registers to control by
  309. * software the SPI pins (and especially the CS).
  310. */
  311. __weak void external_cs_manage(struct udevice *dev, bool on)
  312. {
  313. #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
  314. struct dw_spi_priv *priv = dev_get_priv(dev->parent);
  315. if (!dm_gpio_is_valid(&priv->cs_gpio))
  316. return;
  317. dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
  318. #endif
  319. }
  320. static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  321. const void *dout, void *din, unsigned long flags)
  322. {
  323. struct udevice *bus = dev->parent;
  324. struct dw_spi_priv *priv = dev_get_priv(bus);
  325. const u8 *tx = dout;
  326. u8 *rx = din;
  327. int ret = 0;
  328. u32 cr0 = 0;
  329. u32 val;
  330. u32 cs;
  331. /* spi core configured to do 8 bit transfers */
  332. if (bitlen % 8) {
  333. debug("Non byte aligned SPI transfer.\n");
  334. return -1;
  335. }
  336. /* Start the transaction if necessary. */
  337. if (flags & SPI_XFER_BEGIN)
  338. external_cs_manage(dev, false);
  339. cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
  340. (priv->mode << SPI_MODE_OFFSET) |
  341. (priv->tmode << SPI_TMOD_OFFSET);
  342. if (rx && tx)
  343. priv->tmode = SPI_TMOD_TR;
  344. else if (rx)
  345. priv->tmode = SPI_TMOD_RO;
  346. else
  347. /*
  348. * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
  349. * any data which breaks our logic in poll_transfer() above.
  350. */
  351. priv->tmode = SPI_TMOD_TR;
  352. cr0 &= ~SPI_TMOD_MASK;
  353. cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
  354. priv->len = bitlen >> 3;
  355. debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
  356. priv->tx = (void *)tx;
  357. priv->tx_end = priv->tx + priv->len;
  358. priv->rx = rx;
  359. priv->rx_end = priv->rx + priv->len;
  360. /* Disable controller before writing control registers */
  361. spi_enable_chip(priv, 0);
  362. debug("%s: cr0=%08x\n", __func__, cr0);
  363. /* Reprogram cr0 only if changed */
  364. if (dw_read(priv, DW_SPI_CTRL0) != cr0)
  365. dw_write(priv, DW_SPI_CTRL0, cr0);
  366. /*
  367. * Configure the desired SS (slave select 0...3) in the controller
  368. * The DW SPI controller will activate and deactivate this CS
  369. * automatically. So no cs_activate() etc is needed in this driver.
  370. */
  371. cs = spi_chip_select(dev);
  372. dw_write(priv, DW_SPI_SER, 1 << cs);
  373. /* Enable controller after writing control registers */
  374. spi_enable_chip(priv, 1);
  375. /* Start transfer in a polling loop */
  376. ret = poll_transfer(priv);
  377. /*
  378. * Wait for current transmit operation to complete.
  379. * Otherwise if some data still exists in Tx FIFO it can be
  380. * silently flushed, i.e. dropped on disabling of the controller,
  381. * which happens when writing 0 to DW_SPI_SSIENR which happens
  382. * in the beginning of new transfer.
  383. */
  384. if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
  385. (val & SR_TF_EMPT) && !(val & SR_BUSY),
  386. RX_TIMEOUT * 1000)) {
  387. ret = -ETIMEDOUT;
  388. }
  389. /* Stop the transaction if necessary */
  390. if (flags & SPI_XFER_END)
  391. external_cs_manage(dev, true);
  392. return ret;
  393. }
  394. static int dw_spi_set_speed(struct udevice *bus, uint speed)
  395. {
  396. struct dw_spi_platdata *plat = bus->platdata;
  397. struct dw_spi_priv *priv = dev_get_priv(bus);
  398. u16 clk_div;
  399. if (speed > plat->frequency)
  400. speed = plat->frequency;
  401. /* Disable controller before writing control registers */
  402. spi_enable_chip(priv, 0);
  403. /* clk_div doesn't support odd number */
  404. clk_div = priv->bus_clk_rate / speed;
  405. clk_div = (clk_div + 1) & 0xfffe;
  406. dw_write(priv, DW_SPI_BAUDR, clk_div);
  407. /* Enable controller after writing control registers */
  408. spi_enable_chip(priv, 1);
  409. priv->freq = speed;
  410. debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
  411. priv->freq, clk_div);
  412. return 0;
  413. }
  414. static int dw_spi_set_mode(struct udevice *bus, uint mode)
  415. {
  416. struct dw_spi_priv *priv = dev_get_priv(bus);
  417. /*
  418. * Can't set mode yet. Since this depends on if rx, tx, or
  419. * rx & tx is requested. So we have to defer this to the
  420. * real transfer function.
  421. */
  422. priv->mode = mode;
  423. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  424. return 0;
  425. }
  426. static int dw_spi_remove(struct udevice *bus)
  427. {
  428. struct dw_spi_priv *priv = dev_get_priv(bus);
  429. int ret;
  430. ret = reset_release_bulk(&priv->resets);
  431. if (ret)
  432. return ret;
  433. #if CONFIG_IS_ENABLED(CLK)
  434. ret = clk_disable(&priv->clk);
  435. if (ret)
  436. return ret;
  437. ret = clk_free(&priv->clk);
  438. if (ret)
  439. return ret;
  440. #endif
  441. return 0;
  442. }
  443. static const struct dm_spi_ops dw_spi_ops = {
  444. .xfer = dw_spi_xfer,
  445. .set_speed = dw_spi_set_speed,
  446. .set_mode = dw_spi_set_mode,
  447. /*
  448. * cs_info is not needed, since we require all chip selects to be
  449. * in the device tree explicitly
  450. */
  451. };
  452. static const struct udevice_id dw_spi_ids[] = {
  453. { .compatible = "snps,dw-apb-ssi" },
  454. { }
  455. };
  456. U_BOOT_DRIVER(dw_spi) = {
  457. .name = "dw_spi",
  458. .id = UCLASS_SPI,
  459. .of_match = dw_spi_ids,
  460. .ops = &dw_spi_ops,
  461. .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
  462. .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
  463. .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
  464. .probe = dw_spi_probe,
  465. .remove = dw_spi_remove,
  466. };