sunxi_pwm.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <pwm.h>
  10. #include <regmap.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/pwm.h>
  14. #include <asm/arch/gpio.h>
  15. #include <power/regulator.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define OSC_24MHZ 24000000
  18. struct sunxi_pwm_priv {
  19. struct sunxi_pwm *regs;
  20. bool invert;
  21. u32 prescaler;
  22. };
  23. static const u32 prescaler_table[] = {
  24. 120, /* 0000 */
  25. 180, /* 0001 */
  26. 240, /* 0010 */
  27. 360, /* 0011 */
  28. 480, /* 0100 */
  29. 0, /* 0101 */
  30. 0, /* 0110 */
  31. 0, /* 0111 */
  32. 12000, /* 1000 */
  33. 24000, /* 1001 */
  34. 36000, /* 1010 */
  35. 48000, /* 1011 */
  36. 72000, /* 1100 */
  37. 0, /* 1101 */
  38. 0, /* 1110 */
  39. 1, /* 1111 */
  40. };
  41. static int sunxi_pwm_config_pinmux(void)
  42. {
  43. #ifdef CONFIG_MACH_SUN50I
  44. sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
  45. #endif
  46. return 0;
  47. }
  48. static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
  49. bool polarity)
  50. {
  51. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  52. debug("%s: polarity=%u\n", __func__, polarity);
  53. priv->invert = polarity;
  54. return 0;
  55. }
  56. static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
  57. uint period_ns, uint duty_ns)
  58. {
  59. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  60. struct sunxi_pwm *regs = priv->regs;
  61. int best_prescaler = 0;
  62. u32 v, best_period = 0, duty;
  63. u64 best_scaled_freq = 0;
  64. const u32 nsecs_per_sec = 1000000000U;
  65. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  66. for (int prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
  67. prescaler++) {
  68. u32 period = 0;
  69. u64 scaled_freq = 0;
  70. if (!prescaler_table[prescaler])
  71. continue;
  72. scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
  73. period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
  74. if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) &&
  75. best_period < period) {
  76. best_period = period;
  77. best_scaled_freq = scaled_freq;
  78. best_prescaler = prescaler;
  79. }
  80. }
  81. if (best_period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
  82. debug("%s: failed to find prescaler value\n", __func__);
  83. return -EINVAL;
  84. }
  85. duty = lldiv(best_scaled_freq * duty_ns, nsecs_per_sec);
  86. if (priv->prescaler != best_prescaler) {
  87. /* Mask clock to update prescaler */
  88. v = readl(&regs->ctrl);
  89. v &= ~SUNXI_PWM_CTRL_CLK_GATE;
  90. writel(v, &regs->ctrl);
  91. v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
  92. v |= (best_prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
  93. writel(v, &regs->ctrl);
  94. v |= SUNXI_PWM_CTRL_CLK_GATE;
  95. writel(v, &regs->ctrl);
  96. priv->prescaler = best_prescaler;
  97. }
  98. writel(SUNXI_PWM_CH0_PERIOD_PRD(best_period) |
  99. SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
  100. debug("%s: prescaler: %d, period: %d, duty: %d\n",
  101. __func__, priv->prescaler,
  102. best_period, duty);
  103. return 0;
  104. }
  105. static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  106. {
  107. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  108. struct sunxi_pwm *regs = priv->regs;
  109. u32 v;
  110. debug("%s: Enable '%s'\n", __func__, dev->name);
  111. v = readl(&regs->ctrl);
  112. if (!enable) {
  113. v &= ~SUNXI_PWM_CTRL_ENABLE0;
  114. writel(v, &regs->ctrl);
  115. return 0;
  116. }
  117. sunxi_pwm_config_pinmux();
  118. if (priv->invert)
  119. v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
  120. else
  121. v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
  122. v |= SUNXI_PWM_CTRL_ENABLE0;
  123. writel(v, &regs->ctrl);
  124. return 0;
  125. }
  126. static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
  127. {
  128. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  129. priv->regs = dev_read_addr_ptr(dev);
  130. return 0;
  131. }
  132. static int sunxi_pwm_probe(struct udevice *dev)
  133. {
  134. return 0;
  135. }
  136. static const struct pwm_ops sunxi_pwm_ops = {
  137. .set_invert = sunxi_pwm_set_invert,
  138. .set_config = sunxi_pwm_set_config,
  139. .set_enable = sunxi_pwm_set_enable,
  140. };
  141. static const struct udevice_id sunxi_pwm_ids[] = {
  142. { .compatible = "allwinner,sun5i-a13-pwm" },
  143. { .compatible = "allwinner,sun50i-a64-pwm" },
  144. { }
  145. };
  146. U_BOOT_DRIVER(sunxi_pwm) = {
  147. .name = "sunxi_pwm",
  148. .id = UCLASS_PWM,
  149. .of_match = sunxi_pwm_ids,
  150. .ops = &sunxi_pwm_ops,
  151. .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
  152. .probe = sunxi_pwm_probe,
  153. .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),
  154. };