pwm-mtk.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
  4. *
  5. * Author: Sam Shih <sam.shih@mediatek.com>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <pwm.h>
  11. #include <div64.h>
  12. #include <linux/bitops.h>
  13. #include <linux/io.h>
  14. /* PWM registers and bits definitions */
  15. #define PWMCON 0x00
  16. #define PWMHDUR 0x04
  17. #define PWMLDUR 0x08
  18. #define PWMGDUR 0x0c
  19. #define PWMWAVENUM 0x28
  20. #define PWMDWIDTH 0x2c
  21. #define PWM45DWIDTH_FIXUP 0x30
  22. #define PWMTHRES 0x30
  23. #define PWM45THRES_FIXUP 0x34
  24. #define PWM_CLK_DIV_MAX 7
  25. #define MAX_PWM_NUM 8
  26. #define NSEC_PER_SEC 1000000000L
  27. static const unsigned int mtk_pwm_reg_offset[] = {
  28. 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
  29. };
  30. struct mtk_pwm_soc {
  31. unsigned int num_pwms;
  32. bool pwm45_fixup;
  33. };
  34. struct mtk_pwm_priv {
  35. void __iomem *base;
  36. struct clk top_clk;
  37. struct clk main_clk;
  38. struct clk pwm_clks[MAX_PWM_NUM];
  39. const struct mtk_pwm_soc *soc;
  40. };
  41. static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
  42. {
  43. struct mtk_pwm_priv *priv = dev_get_priv(dev);
  44. u32 offset = mtk_pwm_reg_offset[channel];
  45. writel(val, priv->base + offset + reg);
  46. }
  47. static int mtk_pwm_set_config(struct udevice *dev, uint channel,
  48. uint period_ns, uint duty_ns)
  49. {
  50. struct mtk_pwm_priv *priv = dev_get_priv(dev);
  51. u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty,
  52. reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
  53. u64 resolution;
  54. int ret = 0;
  55. clk_enable(&priv->top_clk);
  56. clk_enable(&priv->main_clk);
  57. /* Using resolution in picosecond gets accuracy higher */
  58. resolution = (u64)NSEC_PER_SEC * 1000;
  59. do_div(resolution, clk_get_rate(&priv->pwm_clks[channel]));
  60. cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
  61. while (cnt_period > 8191) {
  62. resolution *= 2;
  63. clkdiv++;
  64. cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
  65. resolution);
  66. if (clkdiv > PWM_CLK_DIV_MAX && clksel == 0) {
  67. clksel = 1;
  68. clkdiv = 0;
  69. resolution = (u64)NSEC_PER_SEC * 1000 * 1625;
  70. do_div(resolution,
  71. clk_get_rate(&priv->pwm_clks[channel]));
  72. cnt_period = DIV_ROUND_CLOSEST_ULL(
  73. (u64)period_ns * 1000, resolution);
  74. clk_enable(&priv->pwm_clks[channel]);
  75. }
  76. }
  77. if (clkdiv > PWM_CLK_DIV_MAX && clksel == 1) {
  78. printf("pwm period %u not supported\n", period_ns);
  79. return -EINVAL;
  80. }
  81. if (priv->soc->pwm45_fixup && channel > 2) {
  82. /*
  83. * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
  84. * from the other PWMs on MT7623.
  85. */
  86. reg_width = PWM45DWIDTH_FIXUP;
  87. reg_thres = PWM45THRES_FIXUP;
  88. }
  89. cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
  90. if (clksel == 1)
  91. mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | BIT(3) | clkdiv);
  92. else
  93. mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv);
  94. mtk_pwm_w32(dev, channel, reg_width, cnt_period);
  95. mtk_pwm_w32(dev, channel, reg_thres, cnt_duty);
  96. return ret;
  97. };
  98. static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  99. {
  100. struct mtk_pwm_priv *priv = dev_get_priv(dev);
  101. u32 val = 0;
  102. val = readl(priv->base);
  103. if (enable)
  104. val |= BIT(channel);
  105. else
  106. val &= ~BIT(channel);
  107. writel(val, priv->base);
  108. return 0;
  109. };
  110. static int mtk_pwm_probe(struct udevice *dev)
  111. {
  112. struct mtk_pwm_priv *priv = dev_get_priv(dev);
  113. int ret = 0;
  114. int i;
  115. priv->soc = (struct mtk_pwm_soc *)dev_get_driver_data(dev);
  116. priv->base = dev_read_addr_ptr(dev);
  117. if (!priv->base)
  118. return -EINVAL;
  119. ret = clk_get_by_name(dev, "top", &priv->top_clk);
  120. if (ret < 0)
  121. return ret;
  122. ret = clk_get_by_name(dev, "main", &priv->main_clk);
  123. if (ret < 0)
  124. return ret;
  125. for (i = 0; i < priv->soc->num_pwms; i++) {
  126. char name[8];
  127. snprintf(name, sizeof(name), "pwm%d", i + 1);
  128. ret = clk_get_by_name(dev, name, &priv->pwm_clks[i]);
  129. if (ret < 0)
  130. return ret;
  131. }
  132. return ret;
  133. }
  134. static const struct pwm_ops mtk_pwm_ops = {
  135. .set_config = mtk_pwm_set_config,
  136. .set_enable = mtk_pwm_set_enable,
  137. };
  138. static const struct mtk_pwm_soc mt7622_data = {
  139. .num_pwms = 6,
  140. .pwm45_fixup = false,
  141. };
  142. static const struct mtk_pwm_soc mt7623_data = {
  143. .num_pwms = 5,
  144. .pwm45_fixup = true,
  145. };
  146. static const struct mtk_pwm_soc mt7629_data = {
  147. .num_pwms = 1,
  148. .pwm45_fixup = false,
  149. };
  150. static const struct udevice_id mtk_pwm_ids[] = {
  151. { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
  152. { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
  153. { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
  154. { }
  155. };
  156. U_BOOT_DRIVER(mtk_pwm) = {
  157. .name = "mtk_pwm",
  158. .id = UCLASS_PWM,
  159. .of_match = mtk_pwm_ids,
  160. .ops = &mtk_pwm_ops,
  161. .probe = mtk_pwm_probe,
  162. .priv_auto_alloc_size = sizeof(struct mtk_pwm_priv),
  163. };