pcie-cadence-ep.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019
  4. * Written by Ramon Fried <ramon.fried@gmail.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <pci_ep.h>
  10. #include <linux/sizes.h>
  11. #include <linux/log2.h>
  12. #include "pcie-cadence.h"
  13. DECLARE_GLOBAL_DATA_PTR;
  14. static int cdns_write_header(struct udevice *dev, uint fn,
  15. struct pci_ep_header *hdr)
  16. {
  17. struct cdns_pcie *pcie = dev_get_priv(dev);
  18. cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
  19. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
  20. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
  21. hdr->progif_code);
  22. cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
  23. hdr->subclass_code |
  24. hdr->baseclass_code << 8);
  25. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
  26. hdr->cache_line_size);
  27. cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
  28. hdr->subsys_id);
  29. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
  30. hdr->interrupt_pin);
  31. /*
  32. * Vendor ID can only be modified from function 0, all other functions
  33. * use the same vendor ID as function 0.
  34. */
  35. if (fn == 0) {
  36. /* Update the vendor IDs. */
  37. u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
  38. CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
  39. cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
  40. }
  41. return 0;
  42. }
  43. static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
  44. {
  45. struct cdns_pcie *pcie = dev_get_priv(dev);
  46. dma_addr_t bar_phys = ep_bar->phys_addr;
  47. enum pci_barno bar = ep_bar->barno;
  48. int flags = ep_bar->flags;
  49. u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
  50. u64 sz;
  51. /* BAR size is 2^(aperture + 7) */
  52. sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
  53. /*
  54. * roundup_pow_of_two() returns an unsigned long, which is not suited
  55. * for 64bit values.
  56. */
  57. sz = 1ULL << fls64(sz - 1);
  58. aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
  59. if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
  60. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
  61. } else {
  62. bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
  63. bool is_64bits = (sz > SZ_2G) |
  64. !!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
  65. if (is_64bits && (bar & 1))
  66. return -EINVAL;
  67. if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
  68. ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
  69. if (is_64bits && is_prefetch)
  70. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
  71. else if (is_prefetch)
  72. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
  73. else if (is_64bits)
  74. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
  75. else
  76. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
  77. }
  78. addr0 = lower_32_bits(bar_phys);
  79. addr1 = upper_32_bits(bar_phys);
  80. cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
  81. addr0);
  82. cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
  83. addr1);
  84. if (bar < BAR_4) {
  85. reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
  86. b = bar;
  87. } else {
  88. reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
  89. b = bar - BAR_4;
  90. }
  91. cfg = cdns_pcie_readl(pcie, reg);
  92. cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
  93. CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
  94. cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
  95. CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
  96. cdns_pcie_writel(pcie, reg, cfg);
  97. return 0;
  98. }
  99. static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
  100. {
  101. struct cdns_pcie *pcie = dev_get_priv(dev);
  102. u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
  103. /*
  104. * Set the Multiple Message Capable bitfield into the Message Control
  105. * register.
  106. */
  107. u16 flags;
  108. flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
  109. flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
  110. flags |= PCI_MSI_FLAGS_64BIT;
  111. flags &= ~PCI_MSI_FLAGS_MASKBIT;
  112. cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
  113. return 0;
  114. }
  115. static struct pci_ep_ops cdns_pci_ep_ops = {
  116. .write_header = cdns_write_header,
  117. .set_bar = cdns_set_bar,
  118. .set_msi = cdns_set_msi,
  119. };
  120. static int cdns_pci_ep_probe(struct udevice *dev)
  121. {
  122. struct cdns_pcie *pdata = dev_get_priv(dev);
  123. pdata->reg_base = dev_read_addr_ptr(dev);
  124. if (!pdata->reg_base)
  125. return -ENOMEM;
  126. pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  127. "max-functions", 1);
  128. pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  129. "cdns,max-outbound-regions", 8);
  130. return 0;
  131. }
  132. static int cdns_pci_ep_remove(struct udevice *dev)
  133. {
  134. return 0;
  135. }
  136. const struct udevice_id cadence_pci_ep_of_match[] = {
  137. { .compatible = "cdns,cdns-pcie-ep" },
  138. { }
  139. };
  140. U_BOOT_DRIVER(cdns_pcie) = {
  141. .name = "cdns,pcie-ep",
  142. .id = UCLASS_PCI_EP,
  143. .of_match = cadence_pci_ep_of_match,
  144. .ops = &cdns_pci_ep_ops,
  145. .probe = cdns_pci_ep_probe,
  146. .remove = cdns_pci_ep_remove,
  147. .priv_auto_alloc_size = sizeof(struct cdns_pcie),
  148. };