xpedite520x.h 16 KB

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  1. /*
  2. * Copyright 2008 Extreme Engineering Solutions, Inc.
  3. * Copyright 2004-2008 Freescale Semiconductor, Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * xpedite520x board configuration file
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_BOOKE 1 /* BOOKE */
  16. #define CONFIG_E500 1 /* BOOKE e500 family */
  17. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  18. #define CONFIG_MPC8548 1
  19. #define CONFIG_XPEDITE5200 1
  20. #define CONFIG_SYS_BOARD_NAME "XPedite5200"
  21. #define CONFIG_SYS_FORM_PMC_XMC 1
  22. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  23. #ifndef CONFIG_SYS_TEXT_BASE
  24. #define CONFIG_SYS_TEXT_BASE 0xfff80000
  25. #endif
  26. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  27. #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
  28. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  29. #define CONFIG_PCI1 1 /* PCI controller 1 */
  30. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  31. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  32. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  33. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  34. /*
  35. * DDR config
  36. */
  37. #define CONFIG_SYS_FSL_DDR2
  38. #undef CONFIG_FSL_DDR_INTERACTIVE
  39. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  40. #define CONFIG_DDR_SPD
  41. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  42. #define SPD_EEPROM_ADDRESS 0x54
  43. #define CONFIG_NUM_DDR_CONTROLLERS 1
  44. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  45. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  46. #define CONFIG_DDR_ECC
  47. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  48. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  49. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  50. #define CONFIG_VERY_BIG_RAM
  51. #define CONFIG_SYS_CLK_FREQ 66666666
  52. /*
  53. * These can be toggled for performance analysis, otherwise use default.
  54. */
  55. #define CONFIG_L2_CACHE /* toggle L2 cache */
  56. #define CONFIG_BTB /* toggle branch predition */
  57. #define CONFIG_ENABLE_36BIT_PHYS 1
  58. #define CONFIG_SYS_CCSRBAR 0xef000000
  59. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  60. /*
  61. * Diagnostics
  62. */
  63. #define CONFIG_SYS_ALT_MEMTEST
  64. #define CONFIG_SYS_MEMTEST_START 0x10000000
  65. #define CONFIG_SYS_MEMTEST_END 0x20000000
  66. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  67. CONFIG_SYS_POST_I2C)
  68. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
  69. CONFIG_SYS_I2C_EEPROM_ADDR, \
  70. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  71. CONFIG_SYS_I2C_PCA953X_ADDR1, \
  72. CONFIG_SYS_I2C_RTC_ADDR}
  73. /*
  74. * Memory map
  75. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  76. * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
  77. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  78. * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
  79. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  80. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  81. * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
  82. * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
  83. */
  84. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  85. /*
  86. * NAND flash configuration
  87. */
  88. #define CONFIG_SYS_NAND_BASE 0xef800000
  89. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  90. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  91. #define CONFIG_NAND_ACTL
  92. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
  93. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
  94. #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
  95. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  96. /*
  97. * NOR flash configuration
  98. */
  99. #define CONFIG_SYS_FLASH_BASE 0xfc000000
  100. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  101. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  102. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  103. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  104. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  105. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  106. #define CONFIG_FLASH_CFI_DRIVER
  107. #define CONFIG_SYS_FLASH_CFI
  108. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  109. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  110. {0xfbf40000, 0xc0000} }
  111. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  112. /*
  113. * Chip select configuration
  114. */
  115. /* NOR Flash 0 on CS0 */
  116. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  117. BR_PS_16 | \
  118. BR_V)
  119. #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
  120. OR_GPCM_ACS_DIV4 | \
  121. OR_GPCM_SCY_8)
  122. /* NOR Flash 1 on CS1 */
  123. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  124. BR_PS_16 | \
  125. BR_V)
  126. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  127. /* NAND flash on CS2 */
  128. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  129. BR_PS_8 | \
  130. BR_V)
  131. /* NAND flash on CS2 */
  132. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  133. OR_GPCM_BCTLD | \
  134. OR_GPCM_CSNT | \
  135. OR_GPCM_ACS_DIV4 | \
  136. OR_GPCM_SCY_4 | \
  137. OR_GPCM_TRLX | \
  138. OR_GPCM_EHTR)
  139. /* NAND flash on CS3 */
  140. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  141. BR_PS_8 | \
  142. BR_V)
  143. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  144. /*
  145. * Use L1 as initial stack
  146. */
  147. #define CONFIG_SYS_INIT_RAM_LOCK 1
  148. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  149. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
  150. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  151. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  152. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  153. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  154. /*
  155. * Serial Port
  156. */
  157. #define CONFIG_CONS_INDEX 1
  158. #define CONFIG_SYS_NS16550
  159. #define CONFIG_SYS_NS16550_SERIAL
  160. #define CONFIG_SYS_NS16550_REG_SIZE 1
  161. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  162. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  163. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  164. #define CONFIG_SYS_BAUDRATE_TABLE \
  165. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  166. #define CONFIG_BAUDRATE 115200
  167. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  168. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  169. /*
  170. * Use the HUSH parser
  171. */
  172. #define CONFIG_SYS_HUSH_PARSER
  173. /*
  174. * Pass open firmware flat tree
  175. */
  176. #define CONFIG_OF_LIBFDT 1
  177. #define CONFIG_OF_BOARD_SETUP 1
  178. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  179. /*
  180. * I2C
  181. */
  182. #define CONFIG_SYS_I2C
  183. #define CONFIG_SYS_I2C_FSL
  184. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  185. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  186. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  187. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  188. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  189. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  190. /* I2C EEPROM */
  191. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  192. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  193. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  194. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  195. /* I2C RTC */
  196. #define CONFIG_RTC_M41T11 1
  197. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  198. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  199. /* GPIO */
  200. #define CONFIG_PCA953X
  201. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  202. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
  203. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  204. /* PCA957 @ 0x18 */
  205. #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
  206. #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
  207. #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
  208. #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
  209. #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
  210. #define CONFIG_SYS_PCA953X_NVM_WP 0x20
  211. #define CONFIG_SYS_PCA953X_MONARCH 0x40
  212. #define CONFIG_SYS_PCA953X_EREADY 0x80
  213. /* PCA957 @ 0x19 */
  214. #define CONFIG_SYS_PCA953X_P14_IO0 0x01
  215. #define CONFIG_SYS_PCA953X_P14_IO1 0x02
  216. #define CONFIG_SYS_PCA953X_P14_IO2 0x04
  217. #define CONFIG_SYS_PCA953X_P14_IO3 0x08
  218. #define CONFIG_SYS_PCA953X_P14_IO4 0x10
  219. #define CONFIG_SYS_PCA953X_P14_IO5 0x20
  220. #define CONFIG_SYS_PCA953X_P14_IO6 0x40
  221. #define CONFIG_SYS_PCA953X_P14_IO7 0x80
  222. /* 12-bit ADC used to measure CPU diode */
  223. #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
  224. /*
  225. * General PCI
  226. * Memory space is mapped 1-1, but I/O space must start from 0.
  227. */
  228. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  229. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  230. #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
  231. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  232. #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
  233. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
  234. /*
  235. * Networking options
  236. */
  237. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  238. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  239. #define CONFIG_MII 1 /* MII PHY management */
  240. #define CONFIG_ETHPRIME "eTSEC1"
  241. #define CONFIG_TSEC1 1
  242. #define CONFIG_TSEC1_NAME "eTSEC1"
  243. #define TSEC1_FLAGS TSEC_GIGABIT
  244. #define TSEC1_PHY_ADDR 1
  245. #define TSEC1_PHYIDX 0
  246. #define CONFIG_HAS_ETH0
  247. #define CONFIG_TSEC2 1
  248. #define CONFIG_TSEC2_NAME "eTSEC2"
  249. #define TSEC2_FLAGS TSEC_GIGABIT
  250. #define TSEC2_PHY_ADDR 2
  251. #define TSEC2_PHYIDX 0
  252. #define CONFIG_HAS_ETH1
  253. #define CONFIG_TSEC3 1
  254. #define CONFIG_TSEC3_NAME "eTSEC3"
  255. #define TSEC3_FLAGS TSEC_GIGABIT
  256. #define TSEC3_PHY_ADDR 3
  257. #define TSEC3_PHYIDX 0
  258. #define CONFIG_HAS_ETH2
  259. #define CONFIG_TSEC4 1
  260. #define CONFIG_TSEC4_NAME "eTSEC4"
  261. #define TSEC4_FLAGS TSEC_GIGABIT
  262. #define TSEC4_PHY_ADDR 4
  263. #define TSEC4_PHYIDX 0
  264. #define CONFIG_HAS_ETH3
  265. /*
  266. * BOOTP options
  267. */
  268. #define CONFIG_BOOTP_BOOTFILESIZE
  269. #define CONFIG_BOOTP_BOOTPATH
  270. #define CONFIG_BOOTP_GATEWAY
  271. /*
  272. * Command configuration.
  273. */
  274. #include <config_cmd_default.h>
  275. #define CONFIG_CMD_ASKENV
  276. #define CONFIG_CMD_DATE
  277. #define CONFIG_CMD_DHCP
  278. #define CONFIG_CMD_EEPROM
  279. #define CONFIG_CMD_ELF
  280. #define CONFIG_CMD_SAVEENV
  281. #define CONFIG_CMD_FLASH
  282. #define CONFIG_CMD_I2C
  283. #define CONFIG_CMD_JFFS2
  284. #define CONFIG_CMD_MII
  285. #define CONFIG_CMD_NAND
  286. #define CONFIG_CMD_NET
  287. #define CONFIG_CMD_PCA953X
  288. #define CONFIG_CMD_PCA953X_INFO
  289. #define CONFIG_CMD_PCI
  290. #define CONFIG_CMD_PCI_ENUM
  291. #define CONFIG_CMD_PING
  292. #define CONFIG_CMD_SNTP
  293. #define CONFIG_CMD_REGINFO
  294. /*
  295. * Miscellaneous configurable options
  296. */
  297. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  298. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  299. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  300. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  301. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  302. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  303. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  304. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  305. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  306. #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
  307. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  308. #define CONFIG_PREBOOT /* enable preboot variable */
  309. #define CONFIG_FIT 1
  310. #define CONFIG_FIT_VERBOSE 1
  311. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  312. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  313. /*
  314. * For booting Linux, the board info and command line data
  315. * have to be in the first 16 MB of memory, since this is
  316. * the maximum mapped by the Linux kernel during initialization.
  317. */
  318. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  319. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  320. /*
  321. * Environment Configuration
  322. */
  323. #define CONFIG_ENV_IS_IN_FLASH 1
  324. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  325. #define CONFIG_ENV_SIZE 0x8000
  326. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
  327. /*
  328. * Flash memory map:
  329. * fff80000 - ffffffff Pri U-Boot (512 KB)
  330. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  331. * fff00000 - fff3ffff Pri FDT (256KB)
  332. * fef00000 - ffefffff Pri OS image (16MB)
  333. * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
  334. *
  335. * fbf80000 - fbffffff Sec U-Boot (512 KB)
  336. * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
  337. * fbf00000 - fbf3ffff Sec FDT (256KB)
  338. * faf00000 - fbefffff Sec OS image (16MB)
  339. * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
  340. */
  341. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  342. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
  343. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  344. #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
  345. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  346. #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
  347. #define CONFIG_PROG_UBOOT1 \
  348. "$download_cmd $loadaddr $ubootfile; " \
  349. "if test $? -eq 0; then " \
  350. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  351. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  352. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  353. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  354. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  355. "if test $? -ne 0; then " \
  356. "echo PROGRAM FAILED; " \
  357. "else; " \
  358. "echo PROGRAM SUCCEEDED; " \
  359. "fi; " \
  360. "else; " \
  361. "echo DOWNLOAD FAILED; " \
  362. "fi;"
  363. #define CONFIG_PROG_UBOOT2 \
  364. "$download_cmd $loadaddr $ubootfile; " \
  365. "if test $? -eq 0; then " \
  366. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  367. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  368. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  369. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  370. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  371. "if test $? -ne 0; then " \
  372. "echo PROGRAM FAILED; " \
  373. "else; " \
  374. "echo PROGRAM SUCCEEDED; " \
  375. "fi; " \
  376. "else; " \
  377. "echo DOWNLOAD FAILED; " \
  378. "fi;"
  379. #define CONFIG_BOOT_OS_NET \
  380. "$download_cmd $osaddr $osfile; " \
  381. "if test $? -eq 0; then " \
  382. "if test -n $fdtaddr; then " \
  383. "$download_cmd $fdtaddr $fdtfile; " \
  384. "if test $? -eq 0; then " \
  385. "bootm $osaddr - $fdtaddr; " \
  386. "else; " \
  387. "echo FDT DOWNLOAD FAILED; " \
  388. "fi; " \
  389. "else; " \
  390. "bootm $osaddr; " \
  391. "fi; " \
  392. "else; " \
  393. "echo OS DOWNLOAD FAILED; " \
  394. "fi;"
  395. #define CONFIG_PROG_OS1 \
  396. "$download_cmd $osaddr $osfile; " \
  397. "if test $? -eq 0; then " \
  398. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  399. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  400. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  401. "if test $? -ne 0; then " \
  402. "echo OS PROGRAM FAILED; " \
  403. "else; " \
  404. "echo OS PROGRAM SUCCEEDED; " \
  405. "fi; " \
  406. "else; " \
  407. "echo OS DOWNLOAD FAILED; " \
  408. "fi;"
  409. #define CONFIG_PROG_OS2 \
  410. "$download_cmd $osaddr $osfile; " \
  411. "if test $? -eq 0; then " \
  412. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  413. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  414. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  415. "if test $? -ne 0; then " \
  416. "echo OS PROGRAM FAILED; " \
  417. "else; " \
  418. "echo OS PROGRAM SUCCEEDED; " \
  419. "fi; " \
  420. "else; " \
  421. "echo OS DOWNLOAD FAILED; " \
  422. "fi;"
  423. #define CONFIG_PROG_FDT1 \
  424. "$download_cmd $fdtaddr $fdtfile; " \
  425. "if test $? -eq 0; then " \
  426. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  427. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  428. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  429. "if test $? -ne 0; then " \
  430. "echo FDT PROGRAM FAILED; " \
  431. "else; " \
  432. "echo FDT PROGRAM SUCCEEDED; " \
  433. "fi; " \
  434. "else; " \
  435. "echo FDT DOWNLOAD FAILED; " \
  436. "fi;"
  437. #define CONFIG_PROG_FDT2 \
  438. "$download_cmd $fdtaddr $fdtfile; " \
  439. "if test $? -eq 0; then " \
  440. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  441. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  442. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  443. "if test $? -ne 0; then " \
  444. "echo FDT PROGRAM FAILED; " \
  445. "else; " \
  446. "echo FDT PROGRAM SUCCEEDED; " \
  447. "fi; " \
  448. "else; " \
  449. "echo FDT DOWNLOAD FAILED; " \
  450. "fi;"
  451. #define CONFIG_EXTRA_ENV_SETTINGS \
  452. "autoload=yes\0" \
  453. "download_cmd=tftp\0" \
  454. "console_args=console=ttyS0,115200\0" \
  455. "root_args=root=/dev/nfs rw\0" \
  456. "misc_args=ip=on\0" \
  457. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  458. "bootfile=/home/user/file\0" \
  459. "osfile=/home/user/board.uImage\0" \
  460. "fdtfile=/home/user/board.dtb\0" \
  461. "ubootfile=/home/user/u-boot.bin\0" \
  462. "fdtaddr=c00000\0" \
  463. "osaddr=0x1000000\0" \
  464. "loadaddr=0x1000000\0" \
  465. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  466. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  467. "prog_os1="CONFIG_PROG_OS1"\0" \
  468. "prog_os2="CONFIG_PROG_OS2"\0" \
  469. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  470. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  471. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  472. "bootcmd_flash1=run set_bootargs; " \
  473. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  474. "bootcmd_flash2=run set_bootargs; " \
  475. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  476. "bootcmd=run bootcmd_flash1\0"
  477. #endif /* __CONFIG_H */