eb_cpu5282.h 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293
  1. /*
  2. * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
  3. *
  4. * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef _CONFIG_EB_CPU5282_H_
  9. #define _CONFIG_EB_CPU5282_H_
  10. #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  11. /*----------------------------------------------------------------------*
  12. * High Level Configuration Options (easy to change) *
  13. *----------------------------------------------------------------------*/
  14. #define CONFIG_MCF52x2 /* define processor family */
  15. #define CONFIG_M5282 /* define processor type */
  16. #define CONFIG_MISC_INIT_R
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #define CONFIG_BAUDRATE 115200
  20. #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
  21. #define CONFIG_BOOTCOMMAND "printenv"
  22. /*----------------------------------------------------------------------*
  23. * Options *
  24. *----------------------------------------------------------------------*/
  25. #define CONFIG_BOOT_RETRY_TIME -1
  26. #define CONFIG_RESET_TO_RETRY
  27. #define CONFIG_SPLASH_SCREEN
  28. #define CONFIG_HW_WATCHDOG
  29. #define CONFIG_STATUS_LED
  30. #define CONFIG_BOARD_SPECIFIC_LED
  31. #define STATUS_LED_ACTIVE 0
  32. #define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */
  33. #define STATUS_LED_BOOT 0
  34. #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
  35. #define STATUS_LED_STATE STATUS_LED_OFF
  36. /*----------------------------------------------------------------------*
  37. * Configuration for environment *
  38. * Environment is in the second sector of the first 256k of flash *
  39. *----------------------------------------------------------------------*/
  40. #define CONFIG_ENV_ADDR 0xFF040000
  41. #define CONFIG_ENV_SECT_SIZE 0x00020000
  42. #define CONFIG_ENV_IS_IN_FLASH 1
  43. /*
  44. * BOOTP options
  45. */
  46. #define CONFIG_BOOTP_BOOTFILESIZE
  47. #define CONFIG_BOOTP_BOOTPATH
  48. #define CONFIG_BOOTP_GATEWAY
  49. #define CONFIG_BOOTP_HOSTNAME
  50. /*
  51. * Command line configuration.
  52. */
  53. #define CONFIG_CMDLINE_EDITING
  54. #include <config_cmd_default.h>
  55. #undef CONFIG_CMD_LOADB
  56. #define CONFIG_CMD_DATE
  57. #define CONFIG_CMD_DHCP
  58. #define CONFIG_CMD_I2C
  59. #define CONFIG_CMD_LED
  60. #define CONFIG_CMD_MII
  61. #define CONFIG_CMD_NET
  62. #define CONFIG_MCFTMR
  63. #define CONFIG_BOOTDELAY 5
  64. #define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
  65. #define CONFIG_SYS_LONGHELP 1
  66. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  67. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  68. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  69. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  70. #define CONFIG_SYS_LOAD_ADDR 0x20000
  71. #define CONFIG_SYS_MEMTEST_START 0x100000
  72. #define CONFIG_SYS_MEMTEST_END 0x400000
  73. /*#define CONFIG_SYS_DRAM_TEST 1 */
  74. #undef CONFIG_SYS_DRAM_TEST
  75. /*----------------------------------------------------------------------*
  76. * Clock and PLL Configuration *
  77. *----------------------------------------------------------------------*/
  78. #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
  79. /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  80. #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
  81. #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
  82. /*----------------------------------------------------------------------*
  83. * Network *
  84. *----------------------------------------------------------------------*/
  85. #define CONFIG_MCFFEC
  86. #define CONFIG_MII 1
  87. #define CONFIG_MII_INIT 1
  88. #define CONFIG_SYS_DISCOVER_PHY
  89. #define CONFIG_SYS_RX_ETH_BUFFER 8
  90. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  91. #define CONFIG_SYS_FEC0_PINMUX 0
  92. #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  93. #define MCFFEC_TOUT_LOOP 50000
  94. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  95. /*-------------------------------------------------------------------------
  96. * Low Level Configuration Settings
  97. * (address mappings, register initial values, etc.)
  98. * You should know what you are doing if you make changes here.
  99. *-----------------------------------------------------------------------*/
  100. #define CONFIG_SYS_MBAR 0x40000000
  101. /*-----------------------------------------------------------------------
  102. * Definitions for initial stack pointer and data area (in DPRAM)
  103. *-----------------------------------------------------------------------*/
  104. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  105. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  106. #define CONFIG_SYS_GBL_DATA_OFFSET \
  107. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  108. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  109. /*-----------------------------------------------------------------------
  110. * Start addresses for the final memory configuration
  111. * (Set up by the startup code)
  112. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  113. */
  114. #define CONFIG_SYS_SDRAM_BASE0 0x00000000
  115. #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
  116. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
  117. #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
  118. #define CONFIG_SYS_MONITOR_LEN 0x20000
  119. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  120. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  121. /*
  122. * For booting Linux, the board info and command line data
  123. * have to be in the first 8 MB of memory, since this is
  124. * the maximum mapped by the Linux kernel during initialization ??
  125. */
  126. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  127. /*-----------------------------------------------------------------------
  128. * FLASH organization
  129. */
  130. #define CONFIG_FLASH_SHOW_PROGRESS 45
  131. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  132. #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
  133. #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
  134. #define CONFIG_SYS_MAX_FLASH_SECT 128
  135. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  136. #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
  137. #define CONFIG_SYS_FLASH_PROTECTION
  138. #define CONFIG_SYS_FLASH_CFI
  139. #define CONFIG_FLASH_CFI_DRIVER
  140. #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
  141. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  142. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  143. /*-----------------------------------------------------------------------
  144. * Cache Configuration
  145. */
  146. #define CONFIG_SYS_CACHELINE_SIZE 16
  147. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  148. CONFIG_SYS_INIT_RAM_SIZE - 8)
  149. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  150. CONFIG_SYS_INIT_RAM_SIZE - 4)
  151. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
  152. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  153. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  154. CF_ACR_EN | CF_ACR_SM_ALL)
  155. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
  156. CF_CACR_CEIB | CF_CACR_DBWE | \
  157. CF_CACR_EUSP)
  158. /*-----------------------------------------------------------------------
  159. * Memory bank definitions
  160. */
  161. #define CONFIG_SYS_CS0_BASE 0xFF000000
  162. #define CONFIG_SYS_CS0_CTRL 0x00001980
  163. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  164. #define CONFIG_SYS_CS2_BASE 0xE0000000
  165. #define CONFIG_SYS_CS2_CTRL 0x00001980
  166. #define CONFIG_SYS_CS2_MASK 0x000F0001
  167. #define CONFIG_SYS_CS3_BASE 0xE0100000
  168. #define CONFIG_SYS_CS3_CTRL 0x00001980
  169. #define CONFIG_SYS_CS3_MASK 0x000F0001
  170. /*-----------------------------------------------------------------------
  171. * Port configuration
  172. */
  173. #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
  174. #define CONFIG_SYS_PADDR 0x0000000
  175. #define CONFIG_SYS_PADAT 0x0000000
  176. #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
  177. #define CONFIG_SYS_PBDDR 0x0000000
  178. #define CONFIG_SYS_PBDAT 0x0000000
  179. #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
  180. #define CONFIG_SYS_PCDDR 0x0000000
  181. #define CONFIG_SYS_PCDAT 0x0000000
  182. #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
  183. #define CONFIG_SYS_PCDDR 0x0000000
  184. #define CONFIG_SYS_PCDAT 0x0000000
  185. #define CONFIG_SYS_PASPAR 0x0F0F
  186. #define CONFIG_SYS_PEHLPAR 0xC0
  187. #define CONFIG_SYS_PUAPAR 0x0F
  188. #define CONFIG_SYS_DDRUA 0x05
  189. #define CONFIG_SYS_PJPAR 0xFF
  190. /*-----------------------------------------------------------------------
  191. * I2C
  192. */
  193. #define CONFIG_SYS_I2C
  194. #define CONFIG_SYS_I2C_FSL
  195. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
  196. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  197. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  198. #define CONFIG_SYS_FSL_I2C_SLAVE 0
  199. #ifdef CONFIG_CMD_DATE
  200. #define CONFIG_RTC_DS1338
  201. #define CONFIG_I2C_RTC_ADDR 0x68
  202. #endif
  203. /*-----------------------------------------------------------------------
  204. * VIDEO configuration
  205. */
  206. #define CONFIG_VIDEO
  207. #ifdef CONFIG_VIDEO
  208. #define CONFIG_VIDEO_VCXK 1
  209. #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
  210. #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
  211. #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
  212. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
  213. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
  214. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
  215. #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
  216. #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
  217. #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
  218. #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
  219. #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
  220. #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
  221. #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
  222. #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
  223. #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
  224. #endif /* CONFIG_VIDEO */
  225. #endif /* _CONFIG_M5282EVB_H */
  226. /*---------------------------------------------------------------------*/