TQM862M.h 16 KB

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  1. /*
  2. * (C) Copyright 2000-2008
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. * (easy to change)
  15. */
  16. #define CONFIG_MPC860 1
  17. #define CONFIG_MPC860T 1
  18. #define CONFIG_MPC862 1
  19. #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
  20. #define CONFIG_SYS_TEXT_BASE 0x40000000
  21. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  22. #define CONFIG_SYS_SMC_RXBUFLEN 128
  23. #define CONFIG_SYS_MAXIDLE 10
  24. #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  25. #define CONFIG_BOOTCOUNT_LIMIT
  26. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  27. #define CONFIG_BOARD_TYPES 1 /* support board types */
  28. #define CONFIG_PREBOOT "echo;" \
  29. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  30. "echo"
  31. #undef CONFIG_BOOTARGS
  32. #define CONFIG_EXTRA_ENV_SETTINGS \
  33. "netdev=eth0\0" \
  34. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  35. "nfsroot=${serverip}:${rootpath}\0" \
  36. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  37. "addip=setenv bootargs ${bootargs} " \
  38. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  39. ":${hostname}:${netdev}:off panic=1\0" \
  40. "flash_nfs=run nfsargs addip;" \
  41. "bootm ${kernel_addr}\0" \
  42. "flash_self=run ramargs addip;" \
  43. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  44. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
  45. "rootpath=/opt/eldk/ppc_8xx\0" \
  46. "hostname=TQM862M\0" \
  47. "bootfile=TQM862M/uImage\0" \
  48. "fdt_addr=40080000\0" \
  49. "kernel_addr=400A0000\0" \
  50. "ramdisk_addr=40280000\0" \
  51. "u-boot=TQM862M/u-image.bin\0" \
  52. "load=tftp 200000 ${u-boot}\0" \
  53. "update=prot off 40000000 +${filesize};" \
  54. "era 40000000 +${filesize};" \
  55. "cp.b 200000 40000000 ${filesize};" \
  56. "sete filesize;save\0" \
  57. ""
  58. #define CONFIG_BOOTCOMMAND "run flash_self"
  59. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  60. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  61. #undef CONFIG_WATCHDOG /* watchdog disabled */
  62. #define CONFIG_STATUS_LED 1 /* Status LED enabled */
  63. #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  64. /*
  65. * BOOTP options
  66. */
  67. #define CONFIG_BOOTP_SUBNETMASK
  68. #define CONFIG_BOOTP_GATEWAY
  69. #define CONFIG_BOOTP_HOSTNAME
  70. #define CONFIG_BOOTP_BOOTPATH
  71. #define CONFIG_BOOTP_BOOTFILESIZE
  72. #define CONFIG_MAC_PARTITION
  73. #define CONFIG_DOS_PARTITION
  74. #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  75. /*
  76. * Command line configuration.
  77. */
  78. #include <config_cmd_default.h>
  79. #define CONFIG_CMD_ASKENV
  80. #define CONFIG_CMD_DATE
  81. #define CONFIG_CMD_DHCP
  82. #define CONFIG_CMD_ELF
  83. #define CONFIG_CMD_EXT2
  84. #define CONFIG_CMD_IDE
  85. #define CONFIG_CMD_JFFS2
  86. #define CONFIG_CMD_NFS
  87. #define CONFIG_CMD_SNTP
  88. #define CONFIG_NETCONSOLE
  89. /*
  90. * Miscellaneous configurable options
  91. */
  92. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  93. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  94. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  95. #if defined(CONFIG_CMD_KGDB)
  96. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  97. #else
  98. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  99. #endif
  100. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  101. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  102. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  103. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  104. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  105. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  106. /*
  107. * Low Level Configuration Settings
  108. * (address mappings, register initial values, etc.)
  109. * You should know what you are doing if you make changes here.
  110. */
  111. /*-----------------------------------------------------------------------
  112. * Internal Memory Mapped Register
  113. */
  114. #define CONFIG_SYS_IMMR 0xFFF00000
  115. /*-----------------------------------------------------------------------
  116. * Definitions for initial stack pointer and data area (in DPRAM)
  117. */
  118. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  119. #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
  120. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  121. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  122. /*-----------------------------------------------------------------------
  123. * Start addresses for the final memory configuration
  124. * (Set up by the startup code)
  125. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  126. */
  127. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  128. #define CONFIG_SYS_FLASH_BASE 0x40000000
  129. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  130. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  131. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  132. /*
  133. * For booting Linux, the board info and command line data
  134. * have to be in the first 8 MB of memory, since this is
  135. * the maximum mapped by the Linux kernel during initialization.
  136. */
  137. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  138. /*-----------------------------------------------------------------------
  139. * FLASH organization
  140. */
  141. /* use CFI flash driver */
  142. #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
  143. #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
  144. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  145. #define CONFIG_SYS_FLASH_EMPTY_INFO
  146. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  147. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  148. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  149. #define CONFIG_ENV_IS_IN_FLASH 1
  150. #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
  151. #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
  152. #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  153. /* Address and size of Redundant Environment Sector */
  154. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
  155. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  156. #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
  157. #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
  158. /*-----------------------------------------------------------------------
  159. * Dynamic MTD partition support
  160. */
  161. #define CONFIG_CMD_MTDPARTS
  162. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  163. #define CONFIG_FLASH_CFI_MTD
  164. #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
  165. #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
  166. "128k(dtb)," \
  167. "1920k(kernel)," \
  168. "5632(rootfs)," \
  169. "4m(data)"
  170. /*-----------------------------------------------------------------------
  171. * Hardware Information Block
  172. */
  173. #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  174. #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  175. #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  176. /*-----------------------------------------------------------------------
  177. * Cache Configuration
  178. */
  179. #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  180. #if defined(CONFIG_CMD_KGDB)
  181. #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  182. #endif
  183. /*-----------------------------------------------------------------------
  184. * SYPCR - System Protection Control 11-9
  185. * SYPCR can only be written once after reset!
  186. *-----------------------------------------------------------------------
  187. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  188. */
  189. #if defined(CONFIG_WATCHDOG)
  190. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  191. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  192. #else
  193. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  194. #endif
  195. /*-----------------------------------------------------------------------
  196. * SIUMCR - SIU Module Configuration 11-6
  197. *-----------------------------------------------------------------------
  198. * PCMCIA config., multi-function pin tri-state
  199. */
  200. #ifndef CONFIG_CAN_DRIVER
  201. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  202. #else /* we must activate GPL5 in the SIUMCR for CAN */
  203. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  204. #endif /* CONFIG_CAN_DRIVER */
  205. /*-----------------------------------------------------------------------
  206. * TBSCR - Time Base Status and Control 11-26
  207. *-----------------------------------------------------------------------
  208. * Clear Reference Interrupt Status, Timebase freezing enabled
  209. */
  210. #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  211. /*-----------------------------------------------------------------------
  212. * RTCSC - Real-Time Clock Status and Control Register 11-27
  213. *-----------------------------------------------------------------------
  214. */
  215. #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  216. /*-----------------------------------------------------------------------
  217. * PISCR - Periodic Interrupt Status and Control 11-31
  218. *-----------------------------------------------------------------------
  219. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  220. */
  221. #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
  222. /*-----------------------------------------------------------------------
  223. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  224. *-----------------------------------------------------------------------
  225. * Reset PLL lock status sticky bit, timer expired status bit and timer
  226. * interrupt status bit
  227. */
  228. #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  229. /*-----------------------------------------------------------------------
  230. * SCCR - System Clock and reset Control Register 15-27
  231. *-----------------------------------------------------------------------
  232. * Set clock output, timebase and RTC source and divider,
  233. * power management and some other internal clocks
  234. */
  235. #define SCCR_MASK SCCR_EBDF11
  236. #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  237. SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  238. SCCR_DFALCD00)
  239. /*-----------------------------------------------------------------------
  240. * PCMCIA stuff
  241. *-----------------------------------------------------------------------
  242. *
  243. */
  244. #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
  245. #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
  246. #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
  247. #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
  248. #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
  249. #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  250. #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
  251. #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
  252. /*-----------------------------------------------------------------------
  253. * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  254. *-----------------------------------------------------------------------
  255. */
  256. #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
  257. #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  258. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  259. #undef CONFIG_IDE_LED /* LED for ide not supported */
  260. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  261. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  262. #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  263. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  264. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
  265. /* Offset for data I/O */
  266. #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  267. /* Offset for normal register accesses */
  268. #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  269. /* Offset for alternate registers */
  270. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
  271. /*-----------------------------------------------------------------------
  272. *
  273. *-----------------------------------------------------------------------
  274. *
  275. */
  276. #define CONFIG_SYS_DER 0
  277. /*
  278. * Init Memory Controller:
  279. *
  280. * BR0/1 and OR0/1 (FLASH)
  281. */
  282. #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  283. #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
  284. /* used to re-map FLASH both when starting from SRAM or FLASH:
  285. * restrict access enough to keep SRAM working (if any)
  286. * but not too much to meddle with FLASH accesses
  287. */
  288. #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
  289. #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  290. /*
  291. * FLASH timing:
  292. */
  293. #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  294. OR_SCY_3_CLK | OR_EHTR | OR_BI)
  295. #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  296. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  297. #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  298. #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
  299. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  300. #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  301. /*
  302. * BR2/3 and OR2/3 (SDRAM)
  303. *
  304. */
  305. #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  306. #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  307. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  308. /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  309. #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
  310. #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
  311. #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  312. #ifndef CONFIG_CAN_DRIVER
  313. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  314. #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  315. #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  316. #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  317. #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  318. #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
  319. #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
  320. BR_PS_8 | BR_MS_UPMB | BR_V )
  321. #endif /* CONFIG_CAN_DRIVER */
  322. /*
  323. * Memory Periodic Timer Prescaler
  324. *
  325. * The Divider for PTA (refresh timer) configuration is based on an
  326. * example SDRAM configuration (64 MBit, one bank). The adjustment to
  327. * the number of chip selects (NCS) and the actually needed refresh
  328. * rate is done by setting MPTPR.
  329. *
  330. * PTA is calculated from
  331. * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  332. *
  333. * gclk CPU clock (not bus clock!)
  334. * Trefresh Refresh cycle * 4 (four word bursts used)
  335. *
  336. * 4096 Rows from SDRAM example configuration
  337. * 1000 factor s -> ms
  338. * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  339. * 4 Number of refresh cycles per period
  340. * 64 Refresh cycle in ms per number of rows
  341. * --------------------------------------------
  342. * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  343. *
  344. * 50 MHz => 50.000.000 / Divider = 98
  345. * 66 Mhz => 66.000.000 / Divider = 129
  346. * 80 Mhz => 80.000.000 / Divider = 156
  347. * 100 Mhz => 100.000.000 / Divider = 195
  348. */
  349. #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
  350. #define CONFIG_SYS_MAMR_PTA 98
  351. /*
  352. * For 16 MBit, refresh rates could be 31.3 us
  353. * (= 64 ms / 2K = 125 / quad bursts).
  354. * For a simpler initialization, 15.6 us is used instead.
  355. *
  356. * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  357. * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  358. */
  359. #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  360. #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  361. /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  362. #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  363. #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  364. /*
  365. * MAMR settings for SDRAM
  366. */
  367. /* 8 column SDRAM */
  368. #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  369. MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  370. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  371. /* 9 column SDRAM */
  372. #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  373. MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  374. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  375. #define CONFIG_SCC1_ENET
  376. #define CONFIG_FEC_ENET
  377. #define CONFIG_ETHPRIME "SCC"
  378. /* pass open firmware flat tree */
  379. #define CONFIG_OF_LIBFDT 1
  380. #define CONFIG_OF_BOARD_SETUP 1
  381. #define CONFIG_HWCONFIG 1
  382. #endif /* __CONFIG_H */