TQM823L.h 16 KB

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  1. /*
  2. * (C) Copyright 2000-2008
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. * (easy to change)
  15. */
  16. #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  17. #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
  18. #define CONFIG_SYS_TEXT_BASE 0x40000000
  19. #ifdef CONFIG_LCD /* with LCD controller ? */
  20. #define CONFIG_MPC8XX_LCD
  21. #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
  22. #define CONFIG_LCD_INFO 1 /* ... and some board info */
  23. #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
  24. #endif
  25. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  26. #define CONFIG_SYS_SMC_RXBUFLEN 128
  27. #define CONFIG_SYS_MAXIDLE 10
  28. #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  29. #define CONFIG_BOOTCOUNT_LIMIT
  30. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  31. #define CONFIG_BOARD_TYPES 1 /* support board types */
  32. #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  33. #undef CONFIG_BOOTARGS
  34. #define CONFIG_EXTRA_ENV_SETTINGS \
  35. "netdev=eth0\0" \
  36. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  37. "nfsroot=${serverip}:${rootpath}\0" \
  38. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  39. "addip=setenv bootargs ${bootargs} " \
  40. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  41. ":${hostname}:${netdev}:off panic=1\0" \
  42. "flash_nfs=run nfsargs addip;" \
  43. "bootm ${kernel_addr}\0" \
  44. "flash_self=run ramargs addip;" \
  45. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  46. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
  47. "rootpath=/opt/eldk/ppc_8xx\0" \
  48. "hostname=TQM823L\0" \
  49. "bootfile=TQM823L/uImage\0" \
  50. "fdt_addr=40040000\0" \
  51. "kernel_addr=40060000\0" \
  52. "ramdisk_addr=40200000\0" \
  53. "u-boot=TQM823L/u-image.bin\0" \
  54. "load=tftp 200000 ${u-boot}\0" \
  55. "update=prot off 40000000 +${filesize};" \
  56. "era 40000000 +${filesize};" \
  57. "cp.b 200000 40000000 ${filesize};" \
  58. "sete filesize;save\0" \
  59. ""
  60. #define CONFIG_BOOTCOMMAND "run flash_self"
  61. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  62. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  63. #undef CONFIG_WATCHDOG /* watchdog disabled */
  64. #if defined(CONFIG_LCD)
  65. # undef CONFIG_STATUS_LED /* disturbs display */
  66. #else
  67. # define CONFIG_STATUS_LED 1 /* Status LED enabled */
  68. #endif /* CONFIG_LCD */
  69. #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  70. /*
  71. * BOOTP options
  72. */
  73. #define CONFIG_BOOTP_SUBNETMASK
  74. #define CONFIG_BOOTP_GATEWAY
  75. #define CONFIG_BOOTP_HOSTNAME
  76. #define CONFIG_BOOTP_BOOTPATH
  77. #define CONFIG_BOOTP_BOOTFILESIZE
  78. #define CONFIG_MAC_PARTITION
  79. #define CONFIG_DOS_PARTITION
  80. #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  81. /*
  82. * Command line configuration.
  83. */
  84. #include <config_cmd_default.h>
  85. #define CONFIG_CMD_ASKENV
  86. #define CONFIG_CMD_DATE
  87. #define CONFIG_CMD_DHCP
  88. #define CONFIG_CMD_ELF
  89. #define CONFIG_CMD_EXT2
  90. #define CONFIG_CMD_IDE
  91. #define CONFIG_CMD_JFFS2
  92. #define CONFIG_CMD_NFS
  93. #define CONFIG_CMD_SNTP
  94. #ifdef CONFIG_SPLASH_SCREEN
  95. #define CONFIG_CMD_BMP
  96. #endif
  97. #define CONFIG_NETCONSOLE
  98. /*
  99. * Miscellaneous configurable options
  100. */
  101. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  102. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  103. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  104. #if defined(CONFIG_CMD_KGDB)
  105. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  106. #else
  107. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  108. #endif
  109. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  110. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  111. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  112. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  113. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  114. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  115. /*
  116. * Low Level Configuration Settings
  117. * (address mappings, register initial values, etc.)
  118. * You should know what you are doing if you make changes here.
  119. */
  120. /*-----------------------------------------------------------------------
  121. * Internal Memory Mapped Register
  122. */
  123. #define CONFIG_SYS_IMMR 0xFFF00000
  124. /*-----------------------------------------------------------------------
  125. * Definitions for initial stack pointer and data area (in DPRAM)
  126. */
  127. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  128. #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
  129. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  130. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  131. /*-----------------------------------------------------------------------
  132. * Start addresses for the final memory configuration
  133. * (Set up by the startup code)
  134. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  135. */
  136. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  137. #define CONFIG_SYS_FLASH_BASE 0x40000000
  138. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  139. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  140. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  141. /*
  142. * For booting Linux, the board info and command line data
  143. * have to be in the first 8 MB of memory, since this is
  144. * the maximum mapped by the Linux kernel during initialization.
  145. */
  146. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  147. /*-----------------------------------------------------------------------
  148. * FLASH organization
  149. */
  150. /* use CFI flash driver */
  151. #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
  152. #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
  153. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
  154. #define CONFIG_SYS_FLASH_EMPTY_INFO
  155. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  156. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  157. #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
  158. #define CONFIG_ENV_IS_IN_FLASH 1
  159. #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
  160. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  161. /* Address and size of Redundant Environment Sector */
  162. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
  163. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  164. #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
  165. #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
  166. /*-----------------------------------------------------------------------
  167. * Dynamic MTD partition support
  168. */
  169. #define CONFIG_CMD_MTDPARTS
  170. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  171. #define CONFIG_FLASH_CFI_MTD
  172. #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
  173. #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
  174. "128k(dtb)," \
  175. "1664k(kernel)," \
  176. "2m(rootfs)," \
  177. "4m(data)"
  178. /*-----------------------------------------------------------------------
  179. * Hardware Information Block
  180. */
  181. #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  182. #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  183. #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  184. /*-----------------------------------------------------------------------
  185. * Cache Configuration
  186. */
  187. #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  188. #if defined(CONFIG_CMD_KGDB)
  189. #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  190. #endif
  191. /*-----------------------------------------------------------------------
  192. * SYPCR - System Protection Control 11-9
  193. * SYPCR can only be written once after reset!
  194. *-----------------------------------------------------------------------
  195. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  196. */
  197. #if defined(CONFIG_WATCHDOG)
  198. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  199. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  200. #else
  201. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  202. #endif
  203. /*-----------------------------------------------------------------------
  204. * SIUMCR - SIU Module Configuration 11-6
  205. *-----------------------------------------------------------------------
  206. * PCMCIA config., multi-function pin tri-state
  207. */
  208. #ifndef CONFIG_CAN_DRIVER
  209. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  210. #else /* we must activate GPL5 in the SIUMCR for CAN */
  211. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  212. #endif /* CONFIG_CAN_DRIVER */
  213. /*-----------------------------------------------------------------------
  214. * TBSCR - Time Base Status and Control 11-26
  215. *-----------------------------------------------------------------------
  216. * Clear Reference Interrupt Status, Timebase freezing enabled
  217. */
  218. #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  219. /*-----------------------------------------------------------------------
  220. * RTCSC - Real-Time Clock Status and Control Register 11-27
  221. *-----------------------------------------------------------------------
  222. */
  223. #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  224. /*-----------------------------------------------------------------------
  225. * PISCR - Periodic Interrupt Status and Control 11-31
  226. *-----------------------------------------------------------------------
  227. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  228. */
  229. #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
  230. /*-----------------------------------------------------------------------
  231. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  232. *-----------------------------------------------------------------------
  233. * Reset PLL lock status sticky bit, timer expired status bit and timer
  234. * interrupt status bit
  235. */
  236. #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  237. /*-----------------------------------------------------------------------
  238. * SCCR - System Clock and reset Control Register 15-27
  239. *-----------------------------------------------------------------------
  240. * Set clock output, timebase and RTC source and divider,
  241. * power management and some other internal clocks
  242. */
  243. #define SCCR_MASK SCCR_EBDF11
  244. #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  245. SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  246. SCCR_DFALCD00)
  247. /*-----------------------------------------------------------------------
  248. * PCMCIA stuff
  249. *-----------------------------------------------------------------------
  250. *
  251. */
  252. #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
  253. #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
  254. #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
  255. #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
  256. #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
  257. #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  258. #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
  259. #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
  260. /*-----------------------------------------------------------------------
  261. * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  262. *-----------------------------------------------------------------------
  263. */
  264. #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
  265. #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  266. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  267. #undef CONFIG_IDE_LED /* LED for ide not supported */
  268. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  269. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  270. #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  271. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  272. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
  273. /* Offset for data I/O */
  274. #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  275. /* Offset for normal register accesses */
  276. #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  277. /* Offset for alternate registers */
  278. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
  279. /*-----------------------------------------------------------------------
  280. *
  281. *-----------------------------------------------------------------------
  282. *
  283. */
  284. #define CONFIG_SYS_DER 0
  285. /*
  286. * Init Memory Controller:
  287. *
  288. * BR0/1 and OR0/1 (FLASH)
  289. */
  290. #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  291. #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  292. /* used to re-map FLASH both when starting from SRAM or FLASH:
  293. * restrict access enough to keep SRAM working (if any)
  294. * but not too much to meddle with FLASH accesses
  295. */
  296. #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
  297. #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  298. /*
  299. * FLASH timing:
  300. */
  301. #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  302. OR_SCY_3_CLK | OR_EHTR | OR_BI)
  303. #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  304. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  305. #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  306. #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
  307. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  308. #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  309. /*
  310. * BR2/3 and OR2/3 (SDRAM)
  311. *
  312. */
  313. #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  314. #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  315. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  316. /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  317. #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
  318. #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
  319. #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  320. #ifndef CONFIG_CAN_DRIVER
  321. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  322. #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  323. #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  324. #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  325. #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  326. #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
  327. #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
  328. BR_PS_8 | BR_MS_UPMB | BR_V )
  329. #endif /* CONFIG_CAN_DRIVER */
  330. /*
  331. * Memory Periodic Timer Prescaler
  332. *
  333. * The Divider for PTA (refresh timer) configuration is based on an
  334. * example SDRAM configuration (64 MBit, one bank). The adjustment to
  335. * the number of chip selects (NCS) and the actually needed refresh
  336. * rate is done by setting MPTPR.
  337. *
  338. * PTA is calculated from
  339. * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  340. *
  341. * gclk CPU clock (not bus clock!)
  342. * Trefresh Refresh cycle * 4 (four word bursts used)
  343. *
  344. * 4096 Rows from SDRAM example configuration
  345. * 1000 factor s -> ms
  346. * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  347. * 4 Number of refresh cycles per period
  348. * 64 Refresh cycle in ms per number of rows
  349. * --------------------------------------------
  350. * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  351. *
  352. * 50 MHz => 50.000.000 / Divider = 98
  353. * 66 Mhz => 66.000.000 / Divider = 129
  354. * 80 Mhz => 80.000.000 / Divider = 156
  355. */
  356. #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
  357. #define CONFIG_SYS_MAMR_PTA 98
  358. /*
  359. * For 16 MBit, refresh rates could be 31.3 us
  360. * (= 64 ms / 2K = 125 / quad bursts).
  361. * For a simpler initialization, 15.6 us is used instead.
  362. *
  363. * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  364. * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  365. */
  366. #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  367. #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  368. /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  369. #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  370. #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  371. /*
  372. * MAMR settings for SDRAM
  373. */
  374. /* 8 column SDRAM */
  375. #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  376. MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  377. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  378. /* 9 column SDRAM */
  379. #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  380. MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  381. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  382. /* pass open firmware flat tree */
  383. #define CONFIG_OF_LIBFDT 1
  384. #define CONFIG_OF_BOARD_SETUP 1
  385. #define CONFIG_HWCONFIG 1
  386. #endif /* __CONFIG_H */