PM520.h 9.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343
  1. /*
  2. * (C) Copyright 2003-2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. * (easy to change)
  12. */
  13. #define CONFIG_MPC5200
  14. #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  15. #define CONFIG_PM520 1 /* ... on PM520 board */
  16. #define CONFIG_SYS_TEXT_BASE 0xfff00000
  17. #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
  18. #define CONFIG_MISC_INIT_R
  19. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  20. /*
  21. * Serial console configuration
  22. */
  23. #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
  24. #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
  25. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  26. /*
  27. * PCI Mapping:
  28. * 0x40000000 - 0x4fffffff - PCI Memory
  29. * 0x50000000 - 0x50ffffff - PCI IO Space
  30. */
  31. #define CONFIG_PCI 1
  32. #define CONFIG_PCI_PNP 1
  33. #define CONFIG_PCI_SCAN_SHOW 1
  34. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  35. #define CONFIG_PCI_MEM_BUS 0x40000000
  36. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  37. #define CONFIG_PCI_MEM_SIZE 0x10000000
  38. #define CONFIG_PCI_IO_BUS 0x50000000
  39. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  40. #define CONFIG_PCI_IO_SIZE 0x01000000
  41. #define CONFIG_MII 1
  42. #define CONFIG_EEPRO100 1
  43. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  44. #undef CONFIG_NS8382X
  45. /* Partitions */
  46. #define CONFIG_DOS_PARTITION
  47. /* USB */
  48. #if 1
  49. #define CONFIG_USB_OHCI
  50. #define CONFIG_USB_STORAGE
  51. #endif
  52. /*
  53. * BOOTP options
  54. */
  55. #define CONFIG_BOOTP_BOOTFILESIZE
  56. #define CONFIG_BOOTP_BOOTPATH
  57. #define CONFIG_BOOTP_GATEWAY
  58. #define CONFIG_BOOTP_HOSTNAME
  59. /*
  60. * Command line configuration.
  61. */
  62. #include <config_cmd_default.h>
  63. #define CONFIG_CMD_BEDBUG
  64. #define CONFIG_CMD_DATE
  65. #define CONFIG_CMD_DHCP
  66. #define CONFIG_CMD_EEPROM
  67. #define CONFIG_CMD_FAT
  68. #define CONFIG_CMD_I2C
  69. #define CONFIG_CMD_IDE
  70. #define CONFIG_CMD_NFS
  71. #define CONFIG_CMD_SNTP
  72. #define CONFIG_CMD_USB
  73. #define CONFIG_CMD_PCI
  74. /*
  75. * Autobooting
  76. */
  77. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  78. #define CONFIG_PREBOOT "echo;" \
  79. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  80. "echo"
  81. #undef CONFIG_BOOTARGS
  82. #define CONFIG_EXTRA_ENV_SETTINGS \
  83. "netdev=eth0\0" \
  84. "hostname=pm520\0" \
  85. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  86. "nfsroot=${serverip}:${rootpath}\0" \
  87. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  88. "addip=setenv bootargs ${bootargs} " \
  89. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  90. ":${hostname}:${netdev}:off panic=1\0" \
  91. "flash_nfs=run nfsargs addip;" \
  92. "bootm ${kernel_addr}\0" \
  93. "flash_self=run ramargs addip;" \
  94. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  95. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
  96. "rootpath=/opt/eldk30/ppc_82xx\0" \
  97. "bootfile=/tftpboot/PM520/uImage\0" \
  98. ""
  99. #define CONFIG_BOOTCOMMAND "run flash_self"
  100. /*
  101. * IPB Bus clocking configuration.
  102. */
  103. #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
  104. /*
  105. * I2C configuration
  106. */
  107. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  108. #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
  109. #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
  110. #define CONFIG_SYS_I2C_SLAVE 0x7F
  111. /*
  112. * EEPROM configuration
  113. */
  114. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
  115. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  116. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  117. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  118. /*
  119. * RTC configuration
  120. */
  121. #define CONFIG_RTC_PCF8563
  122. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  123. #define CONFIG_SYS_DOC_BASE 0xE0000000
  124. #define CONFIG_SYS_DOC_SIZE 0x00100000
  125. #if defined(CONFIG_BOOT_ROM)
  126. /*
  127. * Flash configuration (8,16 or 32 MB)
  128. * TEXT base always at 0xFFF00000
  129. * ENV_ADDR always at 0xFFF40000
  130. * FLASH_BASE at 0xFA000000 for 64 MB
  131. * 0xFC000000 for 32 MB
  132. * 0xFD000000 for 16 MB
  133. * 0xFD800000 for 8 MB
  134. */
  135. #define CONFIG_SYS_FLASH_BASE 0xFA000000
  136. #define CONFIG_SYS_FLASH_SIZE 0x04000000
  137. #define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
  138. #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
  139. #define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
  140. #else
  141. /*
  142. * Flash configuration (8,16 or 32 MB)
  143. * TEXT base always at 0xFFF00000
  144. * ENV_ADDR always at 0xFFF40000
  145. * FLASH_BASE at 0xFC000000 for 64 MB
  146. * 0xFE000000 for 32 MB
  147. * 0xFF000000 for 16 MB
  148. * 0xFF800000 for 8 MB
  149. */
  150. #define CONFIG_SYS_FLASH_BASE 0xFC000000
  151. #define CONFIG_SYS_FLASH_SIZE 0x04000000
  152. #define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
  153. #endif
  154. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  155. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
  156. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  157. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  158. #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
  159. #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
  160. #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  161. #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
  162. #undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
  163. /*
  164. * Environment settings
  165. */
  166. #define CONFIG_ENV_IS_IN_FLASH 1
  167. #define CONFIG_ENV_SIZE 0x10000
  168. #define CONFIG_ENV_SECT_SIZE 0x40000
  169. #define CONFIG_ENV_OVERWRITE 1
  170. /*
  171. * Memory map
  172. */
  173. #define CONFIG_SYS_MBAR 0xf0000000
  174. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  175. #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  176. /* Use SRAM until RAM will be available */
  177. #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  178. #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
  179. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  180. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  181. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  182. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  183. # define CONFIG_SYS_RAMBOOT 1
  184. #endif
  185. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  186. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  187. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  188. /*
  189. * Ethernet configuration
  190. */
  191. #define CONFIG_MPC5xxx_FEC 1
  192. #define CONFIG_MPC5xxx_FEC_MII100
  193. /*
  194. * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  195. */
  196. /* #define CONFIG_MPC5xxx_FEC_MII10 */
  197. #define CONFIG_PHY_ADDR 0x00
  198. /*
  199. * GPIO configuration
  200. */
  201. #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
  202. /*
  203. * Miscellaneous configurable options
  204. */
  205. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  206. #if defined(CONFIG_CMD_KGDB)
  207. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  208. #else
  209. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  210. #endif
  211. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  212. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  213. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  214. #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  215. #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  216. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  217. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
  218. #if defined(CONFIG_CMD_KGDB)
  219. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  220. #endif
  221. /*
  222. * Various low-level settings
  223. */
  224. #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
  225. #define CONFIG_SYS_HID0_FINAL HID0_ICE
  226. #if defined(CONFIG_BOOT_ROM)
  227. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
  228. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
  229. #define CONFIG_SYS_BOOTCS_CFG 0x00047800
  230. #define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
  231. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
  232. #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
  233. #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
  234. #define CONFIG_SYS_CS1_CFG 0x0004FF00
  235. #else
  236. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  237. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  238. #define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
  239. #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  240. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  241. #define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
  242. #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
  243. #define CONFIG_SYS_CS1_CFG 0x00047800
  244. #endif
  245. #define CONFIG_SYS_CS_BURST 0x00000000
  246. #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
  247. #define CONFIG_SYS_RESET_ADDRESS 0xff000000
  248. /*-----------------------------------------------------------------------
  249. * USB stuff
  250. *-----------------------------------------------------------------------
  251. */
  252. #define CONFIG_USB_CLOCK 0x0001BBBB
  253. #define CONFIG_USB_CONFIG 0x00005000
  254. /*-----------------------------------------------------------------------
  255. * IDE/ATA stuff Supports IDE harddisk
  256. *-----------------------------------------------------------------------
  257. */
  258. #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
  259. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  260. #undef CONFIG_IDE_LED /* LED for ide not supported */
  261. #undef CONFIG_IDE_RESET /* reset for ide supported */
  262. #define CONFIG_IDE_PREINIT
  263. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  264. #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
  265. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  266. #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
  267. /* Offset for data I/O */
  268. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
  269. /* Offset for normal register accesses */
  270. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  271. /* Offset for alternate registers */
  272. #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
  273. /* Interval between registers */
  274. #define CONFIG_SYS_ATA_STRIDE 4
  275. #endif /* __CONFIG_H */