MPC837XEMDS.h 20 KB

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  1. /*
  2. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  3. * Dave Liu <daveliu@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. */
  12. #define CONFIG_E300 1 /* E300 family */
  13. #define CONFIG_MPC83xx 1 /* MPC83xx family */
  14. #define CONFIG_MPC837x 1 /* MPC837x CPU specific */
  15. #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
  16. #define CONFIG_SYS_TEXT_BASE 0xFE000000
  17. /*
  18. * System Clock Setup
  19. */
  20. #ifdef CONFIG_PCISLAVE
  21. #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
  22. #else
  23. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  24. #endif
  25. #ifndef CONFIG_SYS_CLK_FREQ
  26. #define CONFIG_SYS_CLK_FREQ 66000000
  27. #endif
  28. /*
  29. * Hardware Reset Configuration Word
  30. * if CLKIN is 66MHz, then
  31. * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  32. */
  33. #define CONFIG_SYS_HRCW_LOW (\
  34. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  35. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  36. HRCWL_SVCOD_DIV_2 |\
  37. HRCWL_CSB_TO_CLKIN_6X1 |\
  38. HRCWL_CORE_TO_CSB_1_5X1)
  39. #ifdef CONFIG_PCISLAVE
  40. #define CONFIG_SYS_HRCW_HIGH (\
  41. HRCWH_PCI_AGENT |\
  42. HRCWH_PCI1_ARBITER_DISABLE |\
  43. HRCWH_CORE_ENABLE |\
  44. HRCWH_FROM_0XFFF00100 |\
  45. HRCWH_BOOTSEQ_DISABLE |\
  46. HRCWH_SW_WATCHDOG_DISABLE |\
  47. HRCWH_ROM_LOC_LOCAL_16BIT |\
  48. HRCWH_RL_EXT_LEGACY |\
  49. HRCWH_TSEC1M_IN_RGMII |\
  50. HRCWH_TSEC2M_IN_RGMII |\
  51. HRCWH_BIG_ENDIAN |\
  52. HRCWH_LDP_CLEAR)
  53. #else
  54. #define CONFIG_SYS_HRCW_HIGH (\
  55. HRCWH_PCI_HOST |\
  56. HRCWH_PCI1_ARBITER_ENABLE |\
  57. HRCWH_CORE_ENABLE |\
  58. HRCWH_FROM_0X00000100 |\
  59. HRCWH_BOOTSEQ_DISABLE |\
  60. HRCWH_SW_WATCHDOG_DISABLE |\
  61. HRCWH_ROM_LOC_LOCAL_16BIT |\
  62. HRCWH_RL_EXT_LEGACY |\
  63. HRCWH_TSEC1M_IN_RGMII |\
  64. HRCWH_TSEC2M_IN_RGMII |\
  65. HRCWH_BIG_ENDIAN |\
  66. HRCWH_LDP_CLEAR)
  67. #endif
  68. /* Arbiter Configuration Register */
  69. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  70. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
  71. /* System Priority Control Register */
  72. #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
  73. /*
  74. * IP blocks clock configuration
  75. */
  76. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
  77. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
  78. #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
  79. /*
  80. * System IO Config
  81. */
  82. #define CONFIG_SYS_SICRH 0x00000000
  83. #define CONFIG_SYS_SICRL 0x00000000
  84. /*
  85. * Output Buffer Impedance
  86. */
  87. #define CONFIG_SYS_OBIR 0x31100000
  88. #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  89. #define CONFIG_BOARD_EARLY_INIT_R
  90. #define CONFIG_HWCONFIG
  91. /*
  92. * IMMR new address
  93. */
  94. #define CONFIG_SYS_IMMR 0xE0000000
  95. /*
  96. * DDR Setup
  97. */
  98. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
  99. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  100. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  101. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  102. #define CONFIG_SYS_83XX_DDR_USES_CS0
  103. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
  104. | DDRCDR_ODT \
  105. | DDRCDR_Q_DRN)
  106. /* 0x80080001 */ /* ODT 150ohm on SoC */
  107. #undef CONFIG_DDR_ECC /* support DDR ECC function */
  108. #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
  109. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  110. #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  111. #if defined(CONFIG_SPD_EEPROM)
  112. #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
  113. #else
  114. /*
  115. * Manually set up DDR parameters
  116. * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  117. * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  118. */
  119. #define CONFIG_SYS_DDR_SIZE 512 /* MB */
  120. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
  121. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  122. | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
  123. | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
  124. | CSCONFIG_ROW_BIT_14 \
  125. | CSCONFIG_COL_BIT_10)
  126. /* 0x80010202 */
  127. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  128. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  129. | (0 << TIMING_CFG0_WRT_SHIFT) \
  130. | (0 << TIMING_CFG0_RRT_SHIFT) \
  131. | (0 << TIMING_CFG0_WWT_SHIFT) \
  132. | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  133. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  134. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  135. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  136. /* 0x00620802 */
  137. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  138. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  139. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  140. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  141. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  142. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  143. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  144. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  145. /* 0x3935d322 */
  146. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  147. | (6 << TIMING_CFG2_CPO_SHIFT) \
  148. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  149. | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  150. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  151. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  152. | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  153. /* 0x131088c8 */
  154. #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
  155. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  156. /* 0x03E00100 */
  157. #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
  158. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
  159. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  160. | (0x1432 << SDRAM_MODE_SD_SHIFT))
  161. /* ODT 150ohm CL=3, AL=1 on SDRAM */
  162. #define CONFIG_SYS_DDR_MODE2 0x00000000
  163. #endif
  164. /*
  165. * Memory test
  166. */
  167. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  168. #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
  169. #define CONFIG_SYS_MEMTEST_END 0x00140000
  170. /*
  171. * The reserved memory
  172. */
  173. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  174. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  175. #define CONFIG_SYS_RAMBOOT
  176. #else
  177. #undef CONFIG_SYS_RAMBOOT
  178. #endif
  179. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  180. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  181. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  182. /*
  183. * Initial RAM Base Address Setup
  184. */
  185. #define CONFIG_SYS_INIT_RAM_LOCK 1
  186. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  187. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  188. #define CONFIG_SYS_GBL_DATA_OFFSET \
  189. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  190. /*
  191. * Local Bus Configuration & Clock Setup
  192. */
  193. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  194. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
  195. #define CONFIG_SYS_LBC_LBCR 0x00000000
  196. #define CONFIG_FSL_ELBC 1
  197. /*
  198. * FLASH on the Local Bus
  199. */
  200. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  201. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  202. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  203. #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
  204. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  205. /* Window base at flash base */
  206. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  207. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
  208. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  209. | BR_PS_16 /* 16 bit port */ \
  210. | BR_MS_GPCM /* MSEL = GPCM */ \
  211. | BR_V) /* valid */
  212. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  213. | OR_UPM_XAM \
  214. | OR_GPCM_CSNT \
  215. | OR_GPCM_ACS_DIV2 \
  216. | OR_GPCM_XACS \
  217. | OR_GPCM_SCY_15 \
  218. | OR_GPCM_TRLX_SET \
  219. | OR_GPCM_EHTR_SET \
  220. | OR_GPCM_EAD)
  221. /* 0xFE000FF7 */
  222. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  223. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  224. #undef CONFIG_SYS_FLASH_CHECKSUM
  225. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  226. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  227. /*
  228. * BCSR on the Local Bus
  229. */
  230. #define CONFIG_SYS_BCSR 0xF8000000
  231. /* Access window base at BCSR base */
  232. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
  233. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  234. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
  235. | BR_PS_8 \
  236. | BR_MS_GPCM \
  237. | BR_V)
  238. /* 0xF8000801 */
  239. #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
  240. | OR_GPCM_XAM \
  241. | OR_GPCM_CSNT \
  242. | OR_GPCM_XACS \
  243. | OR_GPCM_SCY_15 \
  244. | OR_GPCM_TRLX_SET \
  245. | OR_GPCM_EHTR_SET \
  246. | OR_GPCM_EAD)
  247. /* 0xFFFFE9F7 */
  248. /*
  249. * NAND Flash on the Local Bus
  250. */
  251. #define CONFIG_CMD_NAND 1
  252. #define CONFIG_MTD_NAND_VERIFY_WRITE 1
  253. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  254. #define CONFIG_NAND_FSL_ELBC 1
  255. #define CONFIG_SYS_NAND_BASE 0xE0600000
  256. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
  257. | BR_DECC_CHK_GEN /* Use HW ECC */ \
  258. | BR_PS_8 /* 8 bit port */ \
  259. | BR_MS_FCM /* MSEL = FCM */ \
  260. | BR_V) /* valid */
  261. #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
  262. | OR_FCM_BCTLD \
  263. | OR_FCM_CST \
  264. | OR_FCM_CHT \
  265. | OR_FCM_SCY_1 \
  266. | OR_FCM_RST \
  267. | OR_FCM_TRLX \
  268. | OR_FCM_EHTR)
  269. /* 0xFFFF919E */
  270. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
  271. #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  272. /*
  273. * Serial Port
  274. */
  275. #define CONFIG_CONS_INDEX 1
  276. #define CONFIG_SYS_NS16550
  277. #define CONFIG_SYS_NS16550_SERIAL
  278. #define CONFIG_SYS_NS16550_REG_SIZE 1
  279. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  280. #define CONFIG_SYS_BAUDRATE_TABLE \
  281. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  282. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  283. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  284. /* Use the HUSH parser */
  285. #define CONFIG_SYS_HUSH_PARSER
  286. /* Pass open firmware flat tree */
  287. #define CONFIG_OF_LIBFDT 1
  288. #define CONFIG_OF_BOARD_SETUP 1
  289. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  290. /* I2C */
  291. #define CONFIG_SYS_I2C
  292. #define CONFIG_SYS_I2C_FSL
  293. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  294. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  295. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  296. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  297. /*
  298. * Config on-board RTC
  299. */
  300. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  301. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  302. /*
  303. * General PCI
  304. * Addresses are mapped 1-1.
  305. */
  306. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  307. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  308. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  309. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  310. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  311. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  312. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  313. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  314. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  315. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  316. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  317. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  318. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  319. #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
  320. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
  321. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
  322. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
  323. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  324. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  325. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
  326. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  327. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  328. #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
  329. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
  330. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
  331. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
  332. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  333. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  334. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
  335. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  336. #ifdef CONFIG_PCI
  337. #define CONFIG_PCI_INDIRECT_BRIDGE
  338. #ifndef __ASSEMBLY__
  339. extern int board_pci_host_broken(void);
  340. #endif
  341. #define CONFIG_PCIE
  342. #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
  343. #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
  344. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  345. #undef CONFIG_EEPRO100
  346. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  347. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  348. #endif /* CONFIG_PCI */
  349. /*
  350. * TSEC
  351. */
  352. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  353. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  354. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  355. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  356. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  357. /*
  358. * TSEC ethernet configuration
  359. */
  360. #define CONFIG_MII 1 /* MII PHY management */
  361. #define CONFIG_TSEC1 1
  362. #define CONFIG_TSEC1_NAME "eTSEC0"
  363. #define CONFIG_TSEC2 1
  364. #define CONFIG_TSEC2_NAME "eTSEC1"
  365. #define TSEC1_PHY_ADDR 2
  366. #define TSEC2_PHY_ADDR 3
  367. #define TSEC1_PHY_ADDR_SGMII 8
  368. #define TSEC2_PHY_ADDR_SGMII 4
  369. #define TSEC1_PHYIDX 0
  370. #define TSEC2_PHYIDX 0
  371. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  372. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  373. /* Options are: TSEC[0-1] */
  374. #define CONFIG_ETHPRIME "eTSEC1"
  375. /* SERDES */
  376. #define CONFIG_FSL_SERDES
  377. #define CONFIG_FSL_SERDES1 0xe3000
  378. #define CONFIG_FSL_SERDES2 0xe3100
  379. /*
  380. * SATA
  381. */
  382. #define CONFIG_LIBATA
  383. #define CONFIG_FSL_SATA
  384. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  385. #define CONFIG_SATA1
  386. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  387. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  388. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  389. #define CONFIG_SATA2
  390. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  391. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  392. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  393. #ifdef CONFIG_FSL_SATA
  394. #define CONFIG_LBA48
  395. #define CONFIG_CMD_SATA
  396. #define CONFIG_DOS_PARTITION
  397. #define CONFIG_CMD_EXT2
  398. #endif
  399. /*
  400. * Environment
  401. */
  402. #ifndef CONFIG_SYS_RAMBOOT
  403. #define CONFIG_ENV_IS_IN_FLASH 1
  404. #define CONFIG_ENV_ADDR \
  405. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  406. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  407. #define CONFIG_ENV_SIZE 0x2000
  408. #else
  409. #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
  410. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  411. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  412. #define CONFIG_ENV_SIZE 0x2000
  413. #endif
  414. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  415. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  416. /*
  417. * BOOTP options
  418. */
  419. #define CONFIG_BOOTP_BOOTFILESIZE
  420. #define CONFIG_BOOTP_BOOTPATH
  421. #define CONFIG_BOOTP_GATEWAY
  422. #define CONFIG_BOOTP_HOSTNAME
  423. /*
  424. * Command line configuration.
  425. */
  426. #include <config_cmd_default.h>
  427. #define CONFIG_CMD_PING
  428. #define CONFIG_CMD_I2C
  429. #define CONFIG_CMD_MII
  430. #define CONFIG_CMD_DATE
  431. #if defined(CONFIG_PCI)
  432. #define CONFIG_CMD_PCI
  433. #endif
  434. #if defined(CONFIG_SYS_RAMBOOT)
  435. #undef CONFIG_CMD_SAVEENV
  436. #undef CONFIG_CMD_LOADS
  437. #endif
  438. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  439. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  440. #undef CONFIG_WATCHDOG /* watchdog disabled */
  441. #define CONFIG_MMC 1
  442. #ifdef CONFIG_MMC
  443. #define CONFIG_FSL_ESDHC
  444. #define CONFIG_FSL_ESDHC_PIN_MUX
  445. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  446. #define CONFIG_CMD_MMC
  447. #define CONFIG_GENERIC_MMC
  448. #define CONFIG_CMD_EXT2
  449. #define CONFIG_CMD_FAT
  450. #define CONFIG_DOS_PARTITION
  451. #endif
  452. /*
  453. * Miscellaneous configurable options
  454. */
  455. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  456. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  457. #if defined(CONFIG_CMD_KGDB)
  458. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  459. #else
  460. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  461. #endif
  462. /* Print Buffer Size */
  463. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  464. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  465. /* Boot Argument Buffer Size */
  466. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  467. /*
  468. * For booting Linux, the board info and command line data
  469. * have to be in the first 256 MB of memory, since this is
  470. * the maximum mapped by the Linux kernel during initialization.
  471. */
  472. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  473. /*
  474. * Core HID Setup
  475. */
  476. #define CONFIG_SYS_HID0_INIT 0x000000000
  477. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  478. HID0_ENABLE_INSTRUCTION_CACHE)
  479. #define CONFIG_SYS_HID2 HID2_HBE
  480. /*
  481. * MMU Setup
  482. */
  483. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  484. /* DDR: cache cacheable */
  485. #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
  486. #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
  487. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
  488. | BATL_PP_RW \
  489. | BATL_MEMCOHERENCE)
  490. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
  491. | BATU_BL_256M \
  492. | BATU_VS \
  493. | BATU_VP)
  494. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  495. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  496. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
  497. | BATL_PP_RW \
  498. | BATL_MEMCOHERENCE)
  499. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
  500. | BATU_BL_256M \
  501. | BATU_VS \
  502. | BATU_VP)
  503. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  504. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  505. /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
  506. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
  507. | BATL_PP_RW \
  508. | BATL_CACHEINHIBIT \
  509. | BATL_GUARDEDSTORAGE)
  510. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
  511. | BATU_BL_8M \
  512. | BATU_VS \
  513. | BATU_VP)
  514. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  515. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  516. /* BCSR: cache-inhibit and guarded */
  517. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
  518. | BATL_PP_RW \
  519. | BATL_CACHEINHIBIT \
  520. | BATL_GUARDEDSTORAGE)
  521. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
  522. | BATU_BL_128K \
  523. | BATU_VS \
  524. | BATU_VP)
  525. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  526. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  527. /* FLASH: icache cacheable, but dcache-inhibit and guarded */
  528. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
  529. | BATL_PP_RW \
  530. | BATL_MEMCOHERENCE)
  531. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
  532. | BATU_BL_32M \
  533. | BATU_VS \
  534. | BATU_VP)
  535. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
  536. | BATL_PP_RW \
  537. | BATL_CACHEINHIBIT \
  538. | BATL_GUARDEDSTORAGE)
  539. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  540. /* Stack in dcache: cacheable, no memory coherence */
  541. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
  542. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
  543. | BATU_BL_128K \
  544. | BATU_VS \
  545. | BATU_VP)
  546. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  547. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  548. #ifdef CONFIG_PCI
  549. /* PCI MEM space: cacheable */
  550. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
  551. | BATL_PP_RW \
  552. | BATL_MEMCOHERENCE)
  553. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
  554. | BATU_BL_256M \
  555. | BATU_VS \
  556. | BATU_VP)
  557. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  558. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  559. /* PCI MMIO space: cache-inhibit and guarded */
  560. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
  561. | BATL_PP_RW \
  562. | BATL_CACHEINHIBIT \
  563. | BATL_GUARDEDSTORAGE)
  564. #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
  565. | BATU_BL_256M \
  566. | BATU_VS \
  567. | BATU_VP)
  568. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  569. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  570. #else
  571. #define CONFIG_SYS_IBAT6L (0)
  572. #define CONFIG_SYS_IBAT6U (0)
  573. #define CONFIG_SYS_IBAT7L (0)
  574. #define CONFIG_SYS_IBAT7U (0)
  575. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  576. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  577. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  578. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  579. #endif
  580. #if defined(CONFIG_CMD_KGDB)
  581. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  582. #endif
  583. /*
  584. * Environment Configuration
  585. */
  586. #define CONFIG_ENV_OVERWRITE
  587. #if defined(CONFIG_TSEC_ENET)
  588. #define CONFIG_HAS_ETH0
  589. #define CONFIG_HAS_ETH1
  590. #endif
  591. #define CONFIG_BAUDRATE 115200
  592. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  593. #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  594. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  595. #define CONFIG_EXTRA_ENV_SETTINGS \
  596. "netdev=eth0\0" \
  597. "consoledev=ttyS0\0" \
  598. "ramdiskaddr=1000000\0" \
  599. "ramdiskfile=ramfs.83xx\0" \
  600. "fdtaddr=780000\0" \
  601. "fdtfile=mpc8379_mds.dtb\0" \
  602. ""
  603. #define CONFIG_NFSBOOTCOMMAND \
  604. "setenv bootargs root=/dev/nfs rw " \
  605. "nfsroot=$serverip:$rootpath " \
  606. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  607. "$netdev:off " \
  608. "console=$consoledev,$baudrate $othbootargs;" \
  609. "tftp $loadaddr $bootfile;" \
  610. "tftp $fdtaddr $fdtfile;" \
  611. "bootm $loadaddr - $fdtaddr"
  612. #define CONFIG_RAMBOOTCOMMAND \
  613. "setenv bootargs root=/dev/ram rw " \
  614. "console=$consoledev,$baudrate $othbootargs;" \
  615. "tftp $ramdiskaddr $ramdiskfile;" \
  616. "tftp $loadaddr $bootfile;" \
  617. "tftp $fdtaddr $fdtfile;" \
  618. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  619. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  620. #endif /* __CONFIG_H */