M54418TWR.h 12 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF54418 TWR board.
  3. *
  4. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /*
  10. * board/config.h - configuration options, board specific
  11. */
  12. #ifndef _M54418TWR_H
  13. #define _M54418TWR_H
  14. /*
  15. * High Level Configuration Options
  16. * (easy to change)
  17. */
  18. #define CONFIG_MCF5441x /* define processor family */
  19. #define CONFIG_M54418 /* define processor type */
  20. #define CONFIG_M54418TWR /* M54418TWR board */
  21. #define CONFIG_MCFUART
  22. #define CONFIG_SYS_UART_PORT (0)
  23. #define CONFIG_BAUDRATE 115200
  24. #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  25. #undef CONFIG_WATCHDOG
  26. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  27. /*
  28. * BOOTP options
  29. */
  30. #define CONFIG_BOOTP_BOOTFILESIZE
  31. #define CONFIG_BOOTP_BOOTPATH
  32. #define CONFIG_BOOTP_GATEWAY
  33. #define CONFIG_BOOTP_HOSTNAME
  34. /* Command line configuration */
  35. #include <config_cmd_default.h>
  36. #define CONFIG_CMD_BOOTD
  37. #define CONFIG_CMD_CACHE
  38. #undef CONFIG_CMD_DATE
  39. #define CONFIG_CMD_DHCP
  40. #define CONFIG_CMD_ELF
  41. #undef CONFIG_CMD_FLASH
  42. #undef CONFIG_CMD_I2C
  43. #undef CONFIG_CMD_JFFS2
  44. #undef CONFIG_CMD_UBI
  45. #define CONFIG_CMD_MEMORY
  46. #define CONFIG_CMD_MISC
  47. #define CONFIG_CMD_MII
  48. #undef CONFIG_CMD_NAND
  49. #undef CONFIG_CMD_NAND_YAFFS
  50. #define CONFIG_CMD_NET
  51. #define CONFIG_CMD_NFS
  52. #define CONFIG_CMD_PING
  53. #define CONFIG_CMD_REGINFO
  54. #define CONFIG_CMD_SPI
  55. #define CONFIG_CMD_SF
  56. #undef CONFIG_CMD_IMLS
  57. #undef CONFIG_CMD_LOADB
  58. #undef CONFIG_CMD_LOADS
  59. /*
  60. * NAND FLASH
  61. */
  62. #ifdef CONFIG_CMD_NAND
  63. #define CONFIG_JFFS2_NAND
  64. #define CONFIG_NAND_FSL_NFC
  65. #define CONFIG_SYS_NAND_BASE 0xFC0FC000
  66. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  67. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  68. #define CONFIG_SYS_NAND_SELECT_DEVICE
  69. #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
  70. #endif
  71. /* Network configuration */
  72. #define CONFIG_MCFFEC
  73. #ifdef CONFIG_MCFFEC
  74. #define CONFIG_NET_MULTI 1
  75. #define CONFIG_MII 1
  76. #define CONFIG_MII_INIT 1
  77. #define CONFIG_SYS_DISCOVER_PHY
  78. #define CONFIG_SYS_RX_ETH_BUFFER 2
  79. #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
  80. #define CONFIG_SYS_TX_ETH_BUFFER 2
  81. #define CONFIG_HAS_ETH1
  82. #define CONFIG_SYS_FEC0_PINMUX 0
  83. #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  84. #define CONFIG_SYS_FEC1_PINMUX 0
  85. #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  86. #define MCFFEC_TOUT_LOOP 50000
  87. #define CONFIG_SYS_FEC0_PHYADDR 0
  88. #define CONFIG_SYS_FEC1_PHYADDR 1
  89. #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
  90. #ifdef CONFIG_SYS_NAND_BOOT
  91. #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
  92. "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
  93. "-(jffs2) console=ttyS0,115200"
  94. #else
  95. #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
  96. __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
  97. __stringify(CONFIG_IPADDR) " ip=" \
  98. __stringify(CONFIG_IPADDR) ":" \
  99. __stringify(CONFIG_SERVERIP)":" \
  100. __stringify(CONFIG_GATEWAYIP)": " \
  101. __stringify(CONFIG_NETMASK) \
  102. "::eth0:off:rw console=ttyS0,115200"
  103. #endif
  104. #define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
  105. #define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
  106. #define CONFIG_ETHPRIME "FEC0"
  107. #define CONFIG_IPADDR 192.168.1.2
  108. #define CONFIG_NETMASK 255.255.255.0
  109. #define CONFIG_SERVERIP 192.168.1.1
  110. #define CONFIG_GATEWAYIP 192.168.1.1
  111. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  112. #define CONFIG_SYS_FEC_BUF_USE_SRAM
  113. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  114. #ifndef CONFIG_SYS_DISCOVER_PHY
  115. #define FECDUPLEX FULL
  116. #define FECSPEED _100BASET
  117. #define LINKSTATUS 1
  118. #else
  119. #define LINKSTATUS 0
  120. #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  121. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  122. #endif
  123. #endif /* CONFIG_SYS_DISCOVER_PHY */
  124. #endif
  125. #define CONFIG_HOSTNAME M54418TWR
  126. #if defined(CONFIG_CF_SBF)
  127. /* ST Micro serial flash */
  128. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  129. #define CONFIG_EXTRA_ENV_SETTINGS \
  130. "netdev=eth0\0" \
  131. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  132. "loadaddr=0x40010000\0" \
  133. "sbfhdr=sbfhdr.bin\0" \
  134. "uboot=u-boot.bin\0" \
  135. "load=tftp ${loadaddr} ${sbfhdr};" \
  136. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  137. "upd=run load; run prog\0" \
  138. "prog=sf probe 0:1 1000000 3;" \
  139. "sf erase 0 40000;" \
  140. "sf write ${loadaddr} 0 40000;" \
  141. "save\0" \
  142. ""
  143. #elif defined(CONFIG_SYS_NAND_BOOT)
  144. #define CONFIG_EXTRA_ENV_SETTINGS \
  145. "netdev=eth0\0" \
  146. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  147. "loadaddr=0x40010000\0" \
  148. "u-boot=u-boot.bin\0" \
  149. "load=tftp ${loadaddr} ${u-boot};\0" \
  150. "upd=run load; run prog\0" \
  151. "prog=nand device 0;" \
  152. "nand erase 0 40000;" \
  153. "nb_update ${loadaddr} ${filesize};" \
  154. "save\0" \
  155. ""
  156. #else
  157. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  158. #define CONFIG_EXTRA_ENV_SETTINGS \
  159. "netdev=eth0\0" \
  160. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  161. "loadaddr=40010000\0" \
  162. "u-boot=u-boot.bin\0" \
  163. "load=tftp ${loadaddr) ${u-boot}\0" \
  164. "upd=run load; run prog\0" \
  165. "prog=prot off mram" " ;" \
  166. "cp.b ${loadaddr} 0 ${filesize};" \
  167. "save\0" \
  168. ""
  169. #endif
  170. /* Realtime clock */
  171. #undef CONFIG_MCFRTC
  172. #define CONFIG_RTC_MCFRRTC
  173. #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
  174. /* Timer */
  175. #define CONFIG_MCFTMR
  176. #undef CONFIG_MCFPIT
  177. /* I2c */
  178. #undef CONFIG_SYS_FSL_I2C
  179. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  180. #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  181. /* I2C speed and slave address */
  182. #define CONFIG_SYS_I2C_SPEED 80000
  183. #define CONFIG_SYS_I2C_SLAVE 0x7F
  184. #define CONFIG_SYS_I2C_OFFSET 0x58000
  185. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  186. /* DSPI and Serial Flash */
  187. #define CONFIG_CF_SPI
  188. #define CONFIG_CF_DSPI
  189. #define CONFIG_SERIAL_FLASH
  190. #define CONFIG_HARD_SPI
  191. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  192. #ifdef CONFIG_CMD_SPI
  193. # define CONFIG_SPI_FLASH
  194. # define CONFIG_SPI_FLASH_ATMEL
  195. # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
  196. DSPI_CTAR_PCSSCK_1CLK | \
  197. DSPI_CTAR_PASC(0) | \
  198. DSPI_CTAR_PDT(0) | \
  199. DSPI_CTAR_CSSCK(0) | \
  200. DSPI_CTAR_ASC(0) | \
  201. DSPI_CTAR_DT(1))
  202. # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
  203. # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
  204. #endif
  205. /* Input, PCI, Flexbus, and VCO */
  206. #define CONFIG_EXTRA_CLOCK
  207. #define CONFIG_PRAM 2048 /* 2048 KB */
  208. /* HUSH */
  209. #define CONFIG_SYS_HUSH_PARSER 1
  210. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  211. #define CONFIG_SYS_PROMPT "-> "
  212. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  213. #if defined(CONFIG_CMD_KGDB)
  214. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  215. #else
  216. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  217. #endif
  218. /* Print Buffer Size */
  219. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  220. sizeof(CONFIG_SYS_PROMPT) + 16)
  221. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  222. /* Boot Argument Buffer Size */
  223. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  224. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  225. #define CONFIG_SYS_MBAR 0xFC000000
  226. /*
  227. * Low Level Configuration Settings
  228. * (address mappings, register initial values, etc.)
  229. * You should know what you are doing if you make changes here.
  230. */
  231. /*-----------------------------------------------------------------------
  232. * Definitions for initial stack pointer and data area (in DPRAM)
  233. */
  234. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  235. /* End of used area in internal SRAM */
  236. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  237. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  238. /* size in bytes reserved for initial data */
  239. #define CONFIG_SYS_GBL_DATA_SIZE 256
  240. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
  241. CONFIG_SYS_GBL_DATA_SIZE) - 32)
  242. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  243. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  244. /*-----------------------------------------------------------------------
  245. * Start addresses for the final memory configuration
  246. * (Set up by the startup code)
  247. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  248. */
  249. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  250. #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
  251. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
  252. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  253. #define CONFIG_SYS_DRAM_TEST
  254. #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
  255. #define CONFIG_SERIAL_BOOT
  256. #endif
  257. #if defined(CONFIG_SERIAL_BOOT)
  258. #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
  259. #else
  260. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  261. #endif
  262. #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
  263. /* Reserve 256 kB for Monitor */
  264. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  265. /* Reserve 256 kB for malloc() */
  266. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  267. /*
  268. * For booting Linux, the board info and command line data
  269. * have to be in the first 8 MB of memory, since this is
  270. * the maximum mapped by the Linux kernel during initialization ??
  271. */
  272. /* Initial Memory map for Linux */
  273. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
  274. (CONFIG_SYS_SDRAM_SIZE << 20))
  275. /* Configuration for environment
  276. * Environment is embedded in u-boot in the second sector of the flash
  277. */
  278. #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
  279. #define CONFIG_SYS_NO_FLASH
  280. #define CONFIG_ENV_IS_IN_MRAM 1
  281. #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
  282. #define CONFIG_ENV_SIZE 0x1000
  283. #endif
  284. #if defined(CONFIG_CF_SBF)
  285. #define CONFIG_SYS_NO_FLASH
  286. #define CONFIG_ENV_IS_IN_SPI_FLASH 1
  287. #define CONFIG_ENV_SPI_CS 1
  288. #define CONFIG_ENV_OFFSET 0x40000
  289. #define CONFIG_ENV_SIZE 0x2000
  290. #define CONFIG_ENV_SECT_SIZE 0x10000
  291. #endif
  292. #if defined(CONFIG_SYS_NAND_BOOT)
  293. #define CONFIG_SYS_NO_FLASH
  294. #define CONFIG_ENV_IS_NOWHERE
  295. #define CONFIG_ENV_OFFSET 0x80000
  296. #define CONFIG_ENV_SIZE 0x20000
  297. #define CONFIG_ENV_SECT_SIZE 0x20000
  298. #endif
  299. #undef CONFIG_ENV_OVERWRITE
  300. /* FLASH organization */
  301. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  302. #undef CONFIG_SYS_FLASH_CFI
  303. #ifdef CONFIG_SYS_FLASH_CFI
  304. #define CONFIG_FLASH_CFI_DRIVER 1
  305. /* Max size that the board might have */
  306. #define CONFIG_SYS_FLASH_SIZE 0x1000000
  307. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  308. /* max number of memory banks */
  309. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  310. /* max number of sectors on one chip */
  311. #define CONFIG_SYS_MAX_FLASH_SECT 270
  312. /* "Real" (hardware) sectors protection */
  313. #define CONFIG_SYS_FLASH_PROTECTION
  314. #define CONFIG_SYS_FLASH_CHECKSUM
  315. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  316. #else
  317. /* max number of sectors on one chip */
  318. #define CONFIG_SYS_MAX_FLASH_SECT 270
  319. /* max number of sectors on one chip */
  320. #define CONFIG_SYS_MAX_FLASH_BANKS 0
  321. #endif
  322. /*
  323. * This is setting for JFFS2 support in u-boot.
  324. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  325. */
  326. #ifdef CONFIG_CMD_JFFS2
  327. #define CONFIG_JFFS2_DEV "nand0"
  328. #define CONFIG_JFFS2_PART_OFFSET (0x800000)
  329. #define CONFIG_CMD_MTDPARTS
  330. #define CONFIG_MTD_DEVICE
  331. #define MTDIDS_DEFAULT "nand0=m54418twr.nand"
  332. #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
  333. "7m(kernel)," \
  334. "-(rootfs)"
  335. #endif
  336. #ifdef CONFIG_CMD_UBI
  337. #define CONFIG_CMD_MTDPARTS
  338. #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
  339. #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
  340. #define CONFIG_RBTREE
  341. #define MTDIDS_DEFAULT "nand0=NAND"
  342. #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
  343. "-(ubi)"
  344. #endif
  345. /* Cache Configuration */
  346. #define CONFIG_SYS_CACHELINE_SIZE 16
  347. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  348. CONFIG_SYS_INIT_RAM_SIZE - 8)
  349. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  350. CONFIG_SYS_INIT_RAM_SIZE - 4)
  351. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  352. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  353. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  354. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  355. CF_ACR_EN | CF_ACR_SM_ALL)
  356. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  357. CF_CACR_ICINVA | CF_CACR_EUSP)
  358. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  359. CF_CACR_DEC | CF_CACR_DDCM_P | \
  360. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  361. #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  362. CONFIG_SYS_INIT_RAM_SIZE - 12)
  363. /*-----------------------------------------------------------------------
  364. * Memory bank definitions
  365. */
  366. /*
  367. * CS0 - NOR Flash 16MB
  368. * CS1 - Available
  369. * CS2 - Available
  370. * CS3 - Available
  371. * CS4 - Available
  372. * CS5 - Available
  373. */
  374. /* Flash */
  375. #define CONFIG_SYS_CS0_BASE 0x00000000
  376. #define CONFIG_SYS_CS0_MASK 0x000F0101
  377. #define CONFIG_SYS_CS0_CTRL 0x00001D60
  378. #endif /* _M54418TWR_H */