board.c 31 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  4. *
  5. * Author: Felipe Balbi <balbi@ti.com>
  6. *
  7. * Based on board/ti/dra7xx/evm.c
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <fastboot.h>
  12. #include <fdt_support.h>
  13. #include <image.h>
  14. #include <init.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <palmas.h>
  18. #include <sata.h>
  19. #include <serial.h>
  20. #include <usb.h>
  21. #include <errno.h>
  22. #include <asm/omap_common.h>
  23. #include <asm/omap_sec_common.h>
  24. #include <asm/emif.h>
  25. #include <asm/gpio.h>
  26. #include <asm/arch/gpio.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/dra7xx_iodelay.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/arch/mmc_host_def.h>
  31. #include <asm/arch/sata.h>
  32. #include <asm/arch/gpio.h>
  33. #include <asm/arch/omap.h>
  34. #include <usb.h>
  35. #include <linux/usb/gadget.h>
  36. #include <dwc3-uboot.h>
  37. #include <dwc3-omap-uboot.h>
  38. #include <ti-usb-phy-uboot.h>
  39. #include <mmc.h>
  40. #include <dm/uclass.h>
  41. #include <hang.h>
  42. #include "../common/board_detect.h"
  43. #include "mux_data.h"
  44. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  45. static int board_bootmode_has_emmc(void);
  46. #endif
  47. #define board_is_x15() board_ti_is("BBRDX15_")
  48. #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
  49. !strncmp("B.10", board_ti_get_rev(), 3))
  50. #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
  51. !strncmp("C.00", board_ti_get_rev(), 3))
  52. #define board_is_am572x_evm() board_ti_is("AM572PM_")
  53. #define board_is_am572x_evm_reva3() \
  54. (board_ti_is("AM572PM_") && \
  55. !strncmp("A.30", board_ti_get_rev(), 3))
  56. #define board_is_am574x_idk() board_ti_is("AM574IDK")
  57. #define board_is_am572x_idk() board_ti_is("AM572IDK")
  58. #define board_is_am571x_idk() board_ti_is("AM571IDK")
  59. #define board_is_bbai() board_ti_is("BBONE-AI")
  60. #define board_is_ti_idk() board_is_am574x_idk() || \
  61. board_is_am572x_idk() || \
  62. board_is_am571x_idk()
  63. #ifdef CONFIG_DRIVER_TI_CPSW
  64. #include <cpsw.h>
  65. #endif
  66. DECLARE_GLOBAL_DATA_PTR;
  67. #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
  68. #define GPIO_DDR_VTT_EN GPIO_TO_PIN(7, 11)
  69. /* Touch screen controller to identify the LCD */
  70. #define OSD_TS_FT_BUS_ADDRESS 0
  71. #define OSD_TS_FT_CHIP_ADDRESS 0x38
  72. #define OSD_TS_FT_REG_ID 0xA3
  73. /*
  74. * Touchscreen IDs for various OSD panels
  75. * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  76. */
  77. /* Used on newer osd101t2587 Panels */
  78. #define OSD_TS_FT_ID_5x46 0x54
  79. /* Used on older osd101t2045 Panels */
  80. #define OSD_TS_FT_ID_5606 0x08
  81. #define SYSINFO_BOARD_NAME_MAX_LEN 45
  82. #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
  83. #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
  84. const struct omap_sysinfo sysinfo = {
  85. "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  86. };
  87. static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  88. .dmm_lisa_map_3 = 0x80740300,
  89. .is_ma_present = 0x1
  90. };
  91. static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  92. .dmm_lisa_map_3 = 0x80640100,
  93. .is_ma_present = 0x1
  94. };
  95. static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  96. .dmm_lisa_map_2 = 0xc0600200,
  97. .dmm_lisa_map_3 = 0x80600100,
  98. .is_ma_present = 0x1
  99. };
  100. static const struct dmm_lisa_map_regs bbai_lisa_regs = {
  101. .dmm_lisa_map_3 = 0x80640100,
  102. .is_ma_present = 0x1
  103. };
  104. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  105. {
  106. if (board_is_am571x_idk())
  107. *dmm_lisa_regs = &am571x_idk_lisa_regs;
  108. else if (board_is_am574x_idk())
  109. *dmm_lisa_regs = &am574x_idk_lisa_regs;
  110. else if (board_is_bbai())
  111. *dmm_lisa_regs = &bbai_lisa_regs;
  112. else
  113. *dmm_lisa_regs = &beagle_x15_lisa_regs;
  114. }
  115. static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  116. .sdram_config_init = 0x61851b32,
  117. .sdram_config = 0x61851b32,
  118. .sdram_config2 = 0x08000000,
  119. .ref_ctrl = 0x000040F1,
  120. .ref_ctrl_final = 0x00001035,
  121. .sdram_tim1 = 0xcccf36ab,
  122. .sdram_tim2 = 0x308f7fda,
  123. .sdram_tim3 = 0x409f88a8,
  124. .read_idle_ctrl = 0x00050000,
  125. .zq_config = 0x5007190b,
  126. .temp_alert_config = 0x00000000,
  127. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  128. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  129. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  130. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  131. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  132. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  133. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  134. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  135. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  136. .emif_rd_wr_lvl_ctl = 0x00000000,
  137. .emif_rd_wr_exec_thresh = 0x00000305
  138. };
  139. /* Ext phy ctrl regs 1-35 */
  140. static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  141. 0x10040100,
  142. 0x00910091,
  143. 0x00950095,
  144. 0x009B009B,
  145. 0x009E009E,
  146. 0x00980098,
  147. 0x00340034,
  148. 0x00350035,
  149. 0x00340034,
  150. 0x00310031,
  151. 0x00340034,
  152. 0x007F007F,
  153. 0x007F007F,
  154. 0x007F007F,
  155. 0x007F007F,
  156. 0x007F007F,
  157. 0x00480048,
  158. 0x004A004A,
  159. 0x00520052,
  160. 0x00550055,
  161. 0x00500050,
  162. 0x00000000,
  163. 0x00600020,
  164. 0x40011080,
  165. 0x08102040,
  166. 0x0,
  167. 0x0,
  168. 0x0,
  169. 0x0,
  170. 0x0,
  171. 0x0,
  172. 0x0,
  173. 0x0,
  174. 0x0,
  175. 0x0
  176. };
  177. static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  178. .sdram_config_init = 0x61851b32,
  179. .sdram_config = 0x61851b32,
  180. .sdram_config2 = 0x08000000,
  181. .ref_ctrl = 0x000040F1,
  182. .ref_ctrl_final = 0x00001035,
  183. .sdram_tim1 = 0xcccf36b3,
  184. .sdram_tim2 = 0x308f7fda,
  185. .sdram_tim3 = 0x407f88a8,
  186. .read_idle_ctrl = 0x00050000,
  187. .zq_config = 0x5007190b,
  188. .temp_alert_config = 0x00000000,
  189. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  190. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  191. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  192. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  193. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  194. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  195. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  196. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  197. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  198. .emif_rd_wr_lvl_ctl = 0x00000000,
  199. .emif_rd_wr_exec_thresh = 0x00000305
  200. };
  201. static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  202. 0x10040100,
  203. 0x00910091,
  204. 0x00950095,
  205. 0x009B009B,
  206. 0x009E009E,
  207. 0x00980098,
  208. 0x00340034,
  209. 0x00350035,
  210. 0x00340034,
  211. 0x00310031,
  212. 0x00340034,
  213. 0x007F007F,
  214. 0x007F007F,
  215. 0x007F007F,
  216. 0x007F007F,
  217. 0x007F007F,
  218. 0x00480048,
  219. 0x004A004A,
  220. 0x00520052,
  221. 0x00550055,
  222. 0x00500050,
  223. 0x00000000,
  224. 0x00600020,
  225. 0x40011080,
  226. 0x08102040,
  227. 0x0,
  228. 0x0,
  229. 0x0,
  230. 0x0,
  231. 0x0,
  232. 0x0,
  233. 0x0,
  234. 0x0,
  235. 0x0,
  236. 0x0
  237. };
  238. static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
  239. .sdram_config_init = 0x61863332,
  240. .sdram_config = 0x61863332,
  241. .sdram_config2 = 0x08000000,
  242. .ref_ctrl = 0x0000514d,
  243. .ref_ctrl_final = 0x0000144a,
  244. .sdram_tim1 = 0xd333887c,
  245. .sdram_tim2 = 0x30b37fe3,
  246. .sdram_tim3 = 0x409f8ad8,
  247. .read_idle_ctrl = 0x00050000,
  248. .zq_config = 0x5007190b,
  249. .temp_alert_config = 0x00000000,
  250. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  251. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  252. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  253. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  254. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  255. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  256. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  257. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  258. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  259. .emif_rd_wr_lvl_ctl = 0x00000000,
  260. .emif_rd_wr_exec_thresh = 0x00000305
  261. };
  262. static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
  263. .sdram_config_init = 0x61863332,
  264. .sdram_config = 0x61863332,
  265. .sdram_config2 = 0x08000000,
  266. .ref_ctrl = 0x0000514d,
  267. .ref_ctrl_final = 0x0000144a,
  268. .sdram_tim1 = 0xd333887c,
  269. .sdram_tim2 = 0x30b37fe3,
  270. .sdram_tim3 = 0x409f8ad8,
  271. .read_idle_ctrl = 0x00050000,
  272. .zq_config = 0x5007190b,
  273. .temp_alert_config = 0x00000000,
  274. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  275. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  276. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  277. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  278. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  279. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  280. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  281. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  282. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  283. .emif_rd_wr_lvl_ctl = 0x00000000,
  284. .emif_rd_wr_exec_thresh = 0x00000305,
  285. .emif_ecc_ctrl_reg = 0xD0000001,
  286. .emif_ecc_address_range_1 = 0x3FFF0000,
  287. .emif_ecc_address_range_2 = 0x00000000
  288. };
  289. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  290. {
  291. switch (emif_nr) {
  292. case 1:
  293. if (board_is_am571x_idk())
  294. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  295. else if (board_is_am574x_idk())
  296. *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
  297. else
  298. *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  299. break;
  300. case 2:
  301. if (board_is_am574x_idk())
  302. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  303. else
  304. *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  305. break;
  306. }
  307. }
  308. void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  309. {
  310. switch (emif_nr) {
  311. case 1:
  312. *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  313. *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  314. break;
  315. case 2:
  316. *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  317. *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  318. break;
  319. }
  320. }
  321. struct vcores_data beagle_x15_volts = {
  322. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  323. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  324. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  325. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  326. .mpu.pmic = &tps659038,
  327. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  328. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  329. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  330. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  331. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  332. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  333. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  334. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  335. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  336. .eve.pmic = &tps659038,
  337. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  338. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  339. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  340. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  341. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  342. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  343. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  344. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  345. .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  346. .gpu.pmic = &tps659038,
  347. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  348. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  349. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  350. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  351. .core.addr = TPS659038_REG_ADDR_SMPS6,
  352. .core.pmic = &tps659038,
  353. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  354. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  355. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  356. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  357. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  358. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  359. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  360. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  361. .iva.pmic = &tps659038,
  362. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  363. };
  364. struct vcores_data am572x_idk_volts = {
  365. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  366. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  367. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  368. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  369. .mpu.pmic = &tps659038,
  370. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  371. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  372. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  373. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  374. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  375. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  376. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  377. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  378. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  379. .eve.pmic = &tps659038,
  380. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  381. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  382. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  383. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  384. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  385. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  386. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  387. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  388. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  389. .gpu.pmic = &tps659038,
  390. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  391. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  392. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  393. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  394. .core.addr = TPS659038_REG_ADDR_SMPS7,
  395. .core.pmic = &tps659038,
  396. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  397. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  398. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  399. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  400. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  401. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  402. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  403. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  404. .iva.pmic = &tps659038,
  405. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  406. };
  407. struct vcores_data am571x_idk_volts = {
  408. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  409. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  410. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  411. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  412. .mpu.pmic = &tps659038,
  413. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  414. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  415. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  416. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  417. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  418. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  419. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  420. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  421. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  422. .eve.pmic = &tps659038,
  423. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  424. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  425. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  426. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  427. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  428. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  429. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  430. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  431. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  432. .gpu.pmic = &tps659038,
  433. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  434. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  435. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  436. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  437. .core.addr = TPS659038_REG_ADDR_SMPS7,
  438. .core.pmic = &tps659038,
  439. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  440. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  441. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  442. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  443. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  444. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  445. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  446. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  447. .iva.pmic = &tps659038,
  448. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  449. };
  450. int get_voltrail_opp(int rail_offset)
  451. {
  452. int opp;
  453. switch (rail_offset) {
  454. case VOLT_MPU:
  455. opp = DRA7_MPU_OPP;
  456. break;
  457. case VOLT_CORE:
  458. opp = DRA7_CORE_OPP;
  459. break;
  460. case VOLT_GPU:
  461. opp = DRA7_GPU_OPP;
  462. break;
  463. case VOLT_EVE:
  464. opp = DRA7_DSPEVE_OPP;
  465. break;
  466. case VOLT_IVA:
  467. opp = DRA7_IVA_OPP;
  468. break;
  469. default:
  470. opp = OPP_NOM;
  471. }
  472. return opp;
  473. }
  474. #ifdef CONFIG_SPL_BUILD
  475. /* No env to setup for SPL */
  476. static inline void setup_board_eeprom_env(void) { }
  477. /* Override function to read eeprom information */
  478. void do_board_detect(void)
  479. {
  480. int rc;
  481. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  482. CONFIG_EEPROM_CHIP_ADDRESS);
  483. if (rc)
  484. printf("ti_i2c_eeprom_init failed %d\n", rc);
  485. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  486. rc = board_bootmode_has_emmc();
  487. if (!rc)
  488. rc = ti_emmc_boardid_get();
  489. if (rc)
  490. printf("ti_emmc_boardid_get failed %d\n", rc);
  491. #endif
  492. }
  493. #else /* CONFIG_SPL_BUILD */
  494. /* Override function to read eeprom information: actual i2c read done by SPL*/
  495. void do_board_detect(void)
  496. {
  497. char *bname = NULL;
  498. int rc;
  499. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  500. CONFIG_EEPROM_CHIP_ADDRESS);
  501. if (rc)
  502. printf("ti_i2c_eeprom_init failed %d\n", rc);
  503. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  504. rc = board_bootmode_has_emmc();
  505. if (!rc)
  506. rc = ti_emmc_boardid_get();
  507. if (rc)
  508. printf("ti_emmc_boardid_get failed %d\n", rc);
  509. #endif
  510. if (board_is_x15())
  511. bname = "BeagleBoard X15";
  512. else if (board_is_am572x_evm())
  513. bname = "AM572x EVM";
  514. else if (board_is_am574x_idk())
  515. bname = "AM574x IDK";
  516. else if (board_is_am572x_idk())
  517. bname = "AM572x IDK";
  518. else if (board_is_am571x_idk())
  519. bname = "AM571x IDK";
  520. else if (board_is_bbai())
  521. bname = "BeagleBone AI";
  522. if (bname)
  523. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  524. "Board: %s REV %s\n", bname, board_ti_get_rev());
  525. }
  526. static void setup_board_eeprom_env(void)
  527. {
  528. char *name = "beagle_x15";
  529. int rc;
  530. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  531. CONFIG_EEPROM_CHIP_ADDRESS);
  532. if (rc)
  533. goto invalid_eeprom;
  534. if (board_is_x15()) {
  535. if (board_is_x15_revb1())
  536. name = "beagle_x15_revb1";
  537. else if (board_is_x15_revc())
  538. name = "beagle_x15_revc";
  539. else
  540. name = "beagle_x15";
  541. } else if (board_is_am572x_evm()) {
  542. if (board_is_am572x_evm_reva3())
  543. name = "am57xx_evm_reva3";
  544. else
  545. name = "am57xx_evm";
  546. } else if (board_is_am574x_idk()) {
  547. name = "am574x_idk";
  548. } else if (board_is_am572x_idk()) {
  549. name = "am572x_idk";
  550. } else if (board_is_am571x_idk()) {
  551. name = "am571x_idk";
  552. } else if (board_is_bbai()) {
  553. name = "am5729_beagleboneai";
  554. } else {
  555. printf("Unidentified board claims %s in eeprom header\n",
  556. board_ti_get_name());
  557. }
  558. invalid_eeprom:
  559. set_board_info_env(name);
  560. }
  561. #endif /* CONFIG_SPL_BUILD */
  562. void vcores_init(void)
  563. {
  564. if (board_is_am572x_idk() || board_is_am574x_idk())
  565. *omap_vcores = &am572x_idk_volts;
  566. else if (board_is_am571x_idk())
  567. *omap_vcores = &am571x_idk_volts;
  568. else
  569. *omap_vcores = &beagle_x15_volts;
  570. }
  571. void hw_data_init(void)
  572. {
  573. *prcm = &dra7xx_prcm;
  574. if (is_dra72x())
  575. *dplls_data = &dra72x_dplls;
  576. else if (is_dra76x())
  577. *dplls_data = &dra76x_dplls;
  578. else
  579. *dplls_data = &dra7xx_dplls;
  580. *ctrl = &dra7xx_ctrl;
  581. }
  582. bool am571x_idk_needs_lcd(void)
  583. {
  584. bool needs_lcd;
  585. gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
  586. if (gpio_get_value(GPIO_ETH_LCD))
  587. needs_lcd = false;
  588. else
  589. needs_lcd = true;
  590. gpio_free(GPIO_ETH_LCD);
  591. return needs_lcd;
  592. }
  593. int board_init(void)
  594. {
  595. gpmc_init();
  596. gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  597. return 0;
  598. }
  599. void am57x_idk_lcd_detect(void)
  600. {
  601. int r = -ENODEV;
  602. char *idk_lcd = "no";
  603. struct udevice *dev;
  604. /* Only valid for IDKs */
  605. if (!board_is_ti_idk())
  606. return;
  607. /* Only AM571x IDK has gpio control detect.. so check that */
  608. if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
  609. goto out;
  610. r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
  611. OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
  612. if (r) {
  613. printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
  614. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  615. r);
  616. /* AM572x IDK has no explicit settings for optional LCD kit */
  617. if (board_is_am571x_idk())
  618. printf("%s: Touch screen detect failed: %d!\n",
  619. __func__, r);
  620. goto out;
  621. }
  622. /* Read FT ID */
  623. r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
  624. if (r < 0) {
  625. printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
  626. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  627. OSD_TS_FT_REG_ID, r);
  628. goto out;
  629. }
  630. switch (r) {
  631. case OSD_TS_FT_ID_5606:
  632. idk_lcd = "osd101t2045";
  633. break;
  634. case OSD_TS_FT_ID_5x46:
  635. idk_lcd = "osd101t2587";
  636. break;
  637. default:
  638. printf("%s: Unidentifed Touch screen ID 0x%02x\n",
  639. __func__, r);
  640. /* we will let default be "no lcd" */
  641. }
  642. out:
  643. env_set("idk_lcd", idk_lcd);
  644. /*
  645. * On AM571x_IDK, no Display with J51 set to LCD is considered as an
  646. * invalid configuration and we prevent boot to get user attention.
  647. */
  648. if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
  649. !strncmp(idk_lcd, "no", 2)) {
  650. printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
  651. __func__);
  652. hang();
  653. }
  654. return;
  655. }
  656. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  657. static int device_okay(const char *path)
  658. {
  659. int node;
  660. node = fdt_path_offset(gd->fdt_blob, path);
  661. if (node < 0)
  662. return 0;
  663. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  664. }
  665. #endif
  666. int board_late_init(void)
  667. {
  668. setup_board_eeprom_env();
  669. u8 val;
  670. struct udevice *dev;
  671. /*
  672. * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  673. * This is the POWERHOLD-in-Low behavior.
  674. */
  675. palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  676. /*
  677. * Default FIT boot on HS devices. Non FIT images are not allowed
  678. * on HS devices.
  679. */
  680. if (get_device_type() == HS_DEVICE)
  681. env_set("boot_fit", "1");
  682. /*
  683. * Set the GPIO7 Pad to POWERHOLD. This has higher priority
  684. * over DEV_CTRL.DEV_ON bit. This can be reset in case of
  685. * PMIC Power off. So to be on the safer side set it back
  686. * to POWERHOLD mode irrespective of the current state.
  687. */
  688. palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  689. &val);
  690. val = val | TPS65903X_PAD2_POWERHOLD_MASK;
  691. palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  692. val);
  693. omap_die_id_serial();
  694. omap_set_fastboot_vars();
  695. am57x_idk_lcd_detect();
  696. /* Just probe the potentially supported cdce913 device */
  697. uclass_get_device(UCLASS_CLK, 0, &dev);
  698. if (board_is_bbai())
  699. env_set("console", "ttyS0,115200n8");
  700. #if !defined(CONFIG_SPL_BUILD)
  701. board_ti_set_ethaddr(2);
  702. #endif
  703. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  704. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  705. enable_usb_clocks(0);
  706. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  707. enable_usb_clocks(1);
  708. #endif
  709. return 0;
  710. }
  711. void set_muxconf_regs(void)
  712. {
  713. do_set_mux32((*ctrl)->control_padconf_core_base,
  714. early_padconf, ARRAY_SIZE(early_padconf));
  715. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  716. do_set_mux32((*ctrl)->control_padconf_core_base,
  717. emmc_padconf, ARRAY_SIZE(emmc_padconf));
  718. #endif
  719. }
  720. #ifdef CONFIG_IODELAY_RECALIBRATION
  721. void recalibrate_iodelay(void)
  722. {
  723. const struct pad_conf_entry *pconf;
  724. const struct iodelay_cfg_entry *iod, *delta_iod;
  725. int pconf_sz, iod_sz, delta_iod_sz = 0;
  726. int ret;
  727. if (board_is_am572x_idk()) {
  728. pconf = core_padconf_array_essential_am572x_idk;
  729. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
  730. iod = iodelay_cfg_array_am572x_idk;
  731. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
  732. } else if (board_is_am574x_idk()) {
  733. pconf = core_padconf_array_essential_am574x_idk;
  734. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
  735. iod = iodelay_cfg_array_am574x_idk;
  736. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
  737. } else if (board_is_am571x_idk()) {
  738. pconf = core_padconf_array_essential_am571x_idk;
  739. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
  740. iod = iodelay_cfg_array_am571x_idk;
  741. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
  742. } else if (board_is_bbai()) {
  743. pconf = core_padconf_array_essential_bbai;
  744. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
  745. iod = iodelay_cfg_array_bbai;
  746. iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
  747. } else {
  748. /* Common for X15/GPEVM */
  749. pconf = core_padconf_array_essential_x15;
  750. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
  751. /* There never was an SR1.0 X15.. So.. */
  752. if (omap_revision() == DRA752_ES1_1) {
  753. iod = iodelay_cfg_array_x15_sr1_1;
  754. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
  755. } else {
  756. /* Since full production should switch to SR2.0 */
  757. iod = iodelay_cfg_array_x15_sr2_0;
  758. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
  759. }
  760. }
  761. /* Setup I/O isolation */
  762. ret = __recalibrate_iodelay_start();
  763. if (ret)
  764. goto err;
  765. /* Do the muxing here */
  766. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  767. /* Now do the weird minor deltas that should be safe */
  768. if (board_is_x15() || board_is_am572x_evm()) {
  769. if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
  770. board_is_x15_revc()) {
  771. pconf = core_padconf_array_delta_x15_sr2_0;
  772. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
  773. } else {
  774. pconf = core_padconf_array_delta_x15_sr1_1;
  775. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
  776. }
  777. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  778. }
  779. if (board_is_am571x_idk()) {
  780. if (am571x_idk_needs_lcd()) {
  781. pconf = core_padconf_array_vout_am571x_idk;
  782. pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
  783. delta_iod = iodelay_cfg_array_am571x_idk_4port;
  784. delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
  785. } else {
  786. pconf = core_padconf_array_icss1eth_am571x_idk;
  787. pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
  788. }
  789. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  790. }
  791. /* Setup IOdelay configuration */
  792. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
  793. if (delta_iod_sz)
  794. ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
  795. delta_iod_sz);
  796. err:
  797. /* Closeup.. remove isolation */
  798. __recalibrate_iodelay_end(ret);
  799. }
  800. #endif
  801. #if defined(CONFIG_MMC)
  802. int board_mmc_init(struct bd_info *bis)
  803. {
  804. omap_mmc_init(0, 0, 0, -1, -1);
  805. omap_mmc_init(1, 0, 0, -1, -1);
  806. return 0;
  807. }
  808. static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
  809. .hw_rev = "rev11",
  810. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  811. MMC_CAP(UHS_SDR104),
  812. .max_freq = 96000000,
  813. };
  814. static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
  815. .hw_rev = "rev11",
  816. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  817. MMC_CAP(UHS_SDR104) |
  818. MMC_CAP(UHS_SDR50),
  819. .max_freq = 48000000,
  820. };
  821. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  822. {
  823. switch (omap_revision()) {
  824. case DRA752_ES1_0:
  825. case DRA752_ES1_1:
  826. if (addr == OMAP_HSMMC1_BASE)
  827. return &am57x_es1_1_mmc1_fixups;
  828. else
  829. return &am57x_es1_1_mmc23_fixups;
  830. default:
  831. return NULL;
  832. }
  833. }
  834. #endif
  835. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  836. int spl_start_uboot(void)
  837. {
  838. /* break into full u-boot on 'c' */
  839. if (serial_tstc() && serial_getc() == 'c')
  840. return 1;
  841. #ifdef CONFIG_SPL_ENV_SUPPORT
  842. env_init();
  843. env_load();
  844. if (env_get_yesno("boot_os") != 1)
  845. return 1;
  846. #endif
  847. return 0;
  848. }
  849. #endif
  850. #ifdef CONFIG_DRIVER_TI_CPSW
  851. /* Delay value to add to calibrated value */
  852. #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  853. #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  854. #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  855. #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  856. #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  857. #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  858. #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  859. #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  860. #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  861. #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  862. static void cpsw_control(int enabled)
  863. {
  864. /* VTP can be added here */
  865. }
  866. static struct cpsw_slave_data cpsw_slaves[] = {
  867. {
  868. .slave_reg_ofs = 0x208,
  869. .sliver_reg_ofs = 0xd80,
  870. .phy_addr = 1,
  871. },
  872. {
  873. .slave_reg_ofs = 0x308,
  874. .sliver_reg_ofs = 0xdc0,
  875. .phy_addr = 2,
  876. },
  877. };
  878. static struct cpsw_platform_data cpsw_data = {
  879. .mdio_base = CPSW_MDIO_BASE,
  880. .cpsw_base = CPSW_BASE,
  881. .mdio_div = 0xff,
  882. .channels = 8,
  883. .cpdma_reg_ofs = 0x800,
  884. .slaves = 1,
  885. .slave_data = cpsw_slaves,
  886. .ale_reg_ofs = 0xd00,
  887. .ale_entries = 1024,
  888. .host_port_reg_ofs = 0x108,
  889. .hw_stats_reg_ofs = 0x900,
  890. .bd_ram_ofs = 0x2000,
  891. .mac_control = (1 << 5),
  892. .control = cpsw_control,
  893. .host_port_num = 0,
  894. .version = CPSW_CTRL_VERSION_2,
  895. };
  896. static u64 mac_to_u64(u8 mac[6])
  897. {
  898. int i;
  899. u64 addr = 0;
  900. for (i = 0; i < 6; i++) {
  901. addr <<= 8;
  902. addr |= mac[i];
  903. }
  904. return addr;
  905. }
  906. static void u64_to_mac(u64 addr, u8 mac[6])
  907. {
  908. mac[5] = addr;
  909. mac[4] = addr >> 8;
  910. mac[3] = addr >> 16;
  911. mac[2] = addr >> 24;
  912. mac[1] = addr >> 32;
  913. mac[0] = addr >> 40;
  914. }
  915. int board_eth_init(struct bd_info *bis)
  916. {
  917. int ret;
  918. uint8_t mac_addr[6];
  919. uint32_t mac_hi, mac_lo;
  920. uint32_t ctrl_val;
  921. int i;
  922. u64 mac1, mac2;
  923. u8 mac_addr1[6], mac_addr2[6];
  924. int num_macs;
  925. /* try reading mac address from efuse */
  926. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  927. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  928. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  929. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  930. mac_addr[2] = mac_hi & 0xFF;
  931. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  932. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  933. mac_addr[5] = mac_lo & 0xFF;
  934. if (!env_get("ethaddr")) {
  935. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  936. if (is_valid_ethaddr(mac_addr))
  937. eth_env_set_enetaddr("ethaddr", mac_addr);
  938. }
  939. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  940. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  941. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  942. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  943. mac_addr[2] = mac_hi & 0xFF;
  944. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  945. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  946. mac_addr[5] = mac_lo & 0xFF;
  947. if (!env_get("eth1addr")) {
  948. if (is_valid_ethaddr(mac_addr))
  949. eth_env_set_enetaddr("eth1addr", mac_addr);
  950. }
  951. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  952. ctrl_val |= 0x22;
  953. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  954. /* The phy address for the AM57xx IDK are different than x15 */
  955. if (board_is_am572x_idk() || board_is_am571x_idk() ||
  956. board_is_am574x_idk()) {
  957. cpsw_data.slave_data[0].phy_addr = 0;
  958. cpsw_data.slave_data[1].phy_addr = 1;
  959. }
  960. ret = cpsw_register(&cpsw_data);
  961. if (ret < 0)
  962. printf("Error %d registering CPSW switch\n", ret);
  963. /*
  964. * Export any Ethernet MAC addresses from EEPROM.
  965. * On AM57xx the 2 MAC addresses define the address range
  966. */
  967. board_ti_get_eth_mac_addr(0, mac_addr1);
  968. board_ti_get_eth_mac_addr(1, mac_addr2);
  969. if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
  970. mac1 = mac_to_u64(mac_addr1);
  971. mac2 = mac_to_u64(mac_addr2);
  972. /* must contain an address range */
  973. num_macs = mac2 - mac1 + 1;
  974. /* <= 50 to protect against user programming error */
  975. if (num_macs > 0 && num_macs <= 50) {
  976. for (i = 0; i < num_macs; i++) {
  977. u64_to_mac(mac1 + i, mac_addr);
  978. if (is_valid_ethaddr(mac_addr)) {
  979. eth_env_set_enetaddr_by_index("eth",
  980. i + 2,
  981. mac_addr);
  982. }
  983. }
  984. }
  985. }
  986. return ret;
  987. }
  988. #endif
  989. #ifdef CONFIG_BOARD_EARLY_INIT_F
  990. /* VTT regulator enable */
  991. static inline void vtt_regulator_enable(void)
  992. {
  993. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  994. return;
  995. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  996. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  997. }
  998. int board_early_init_f(void)
  999. {
  1000. vtt_regulator_enable();
  1001. return 0;
  1002. }
  1003. #endif
  1004. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  1005. int ft_board_setup(void *blob, struct bd_info *bd)
  1006. {
  1007. ft_cpu_setup(blob, bd);
  1008. return 0;
  1009. }
  1010. #endif
  1011. #ifdef CONFIG_SPL_LOAD_FIT
  1012. int board_fit_config_name_match(const char *name)
  1013. {
  1014. if (board_is_x15()) {
  1015. if (board_is_x15_revb1()) {
  1016. if (!strcmp(name, "am57xx-beagle-x15-revb1"))
  1017. return 0;
  1018. } else if (board_is_x15_revc()) {
  1019. if (!strcmp(name, "am57xx-beagle-x15-revc"))
  1020. return 0;
  1021. } else if (!strcmp(name, "am57xx-beagle-x15")) {
  1022. return 0;
  1023. }
  1024. } else if (board_is_am572x_evm() &&
  1025. !strcmp(name, "am57xx-beagle-x15")) {
  1026. return 0;
  1027. } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
  1028. return 0;
  1029. } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
  1030. return 0;
  1031. } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
  1032. return 0;
  1033. } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
  1034. return 0;
  1035. }
  1036. return -1;
  1037. }
  1038. #endif
  1039. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  1040. int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
  1041. {
  1042. if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
  1043. return -ENOTSUPP;
  1044. printf("Setting reboot to fastboot flag ...\n");
  1045. env_set("dofastboot", "1");
  1046. env_save();
  1047. return 0;
  1048. }
  1049. #endif
  1050. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  1051. static int board_bootmode_has_emmc(void)
  1052. {
  1053. /* Check that boot mode is same as BBAI */
  1054. if (gd->arch.omap_boot_mode != 2)
  1055. return -EIO;
  1056. return 0;
  1057. }
  1058. #endif
  1059. #ifdef CONFIG_TI_SECURE_DEVICE
  1060. void board_fit_image_post_process(void **p_image, size_t *p_size)
  1061. {
  1062. secure_boot_verify_image(p_image, p_size);
  1063. }
  1064. void board_tee_image_process(ulong tee_image, size_t tee_size)
  1065. {
  1066. secure_tee_install((u32)tee_image);
  1067. }
  1068. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  1069. #endif