dwmmc.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. */
  6. #ifndef __DWMMC_HW_H
  7. #define __DWMMC_HW_H
  8. #include <asm/io.h>
  9. #include <mmc.h>
  10. #define DWMCI_CTRL 0x000
  11. #define DWMCI_PWREN 0x004
  12. #define DWMCI_CLKDIV 0x008
  13. #define DWMCI_CLKSRC 0x00C
  14. #define DWMCI_CLKENA 0x010
  15. #define DWMCI_TMOUT 0x014
  16. #define DWMCI_CTYPE 0x018
  17. #define DWMCI_BLKSIZ 0x01C
  18. #define DWMCI_BYTCNT 0x020
  19. #define DWMCI_INTMASK 0x024
  20. #define DWMCI_CMDARG 0x028
  21. #define DWMCI_CMD 0x02C
  22. #define DWMCI_RESP0 0x030
  23. #define DWMCI_RESP1 0x034
  24. #define DWMCI_RESP2 0x038
  25. #define DWMCI_RESP3 0x03C
  26. #define DWMCI_MINTSTS 0x040
  27. #define DWMCI_RINTSTS 0x044
  28. #define DWMCI_STATUS 0x048
  29. #define DWMCI_FIFOTH 0x04C
  30. #define DWMCI_CDETECT 0x050
  31. #define DWMCI_WRTPRT 0x054
  32. #define DWMCI_GPIO 0x058
  33. #define DWMCI_TCMCNT 0x05C
  34. #define DWMCI_TBBCNT 0x060
  35. #define DWMCI_DEBNCE 0x064
  36. #define DWMCI_USRID 0x068
  37. #define DWMCI_VERID 0x06C
  38. #define DWMCI_HCON 0x070
  39. #define DWMCI_UHS_REG 0x074
  40. #define DWMCI_BMOD 0x080
  41. #define DWMCI_PLDMND 0x084
  42. #define DWMCI_DBADDR 0x088
  43. #define DWMCI_IDSTS 0x08C
  44. #define DWMCI_IDINTEN 0x090
  45. #define DWMCI_DSCADDR 0x094
  46. #define DWMCI_BUFADDR 0x098
  47. #define DWMCI_DATA 0x200
  48. /* Interrupt Mask register */
  49. #define DWMCI_INTMSK_ALL 0xffffffff
  50. #define DWMCI_INTMSK_RE (1 << 1)
  51. #define DWMCI_INTMSK_CDONE (1 << 2)
  52. #define DWMCI_INTMSK_DTO (1 << 3)
  53. #define DWMCI_INTMSK_TXDR (1 << 4)
  54. #define DWMCI_INTMSK_RXDR (1 << 5)
  55. #define DWMCI_INTMSK_DCRC (1 << 7)
  56. #define DWMCI_INTMSK_RTO (1 << 8)
  57. #define DWMCI_INTMSK_DRTO (1 << 9)
  58. #define DWMCI_INTMSK_HTO (1 << 10)
  59. #define DWMCI_INTMSK_FRUN (1 << 11)
  60. #define DWMCI_INTMSK_HLE (1 << 12)
  61. #define DWMCI_INTMSK_SBE (1 << 13)
  62. #define DWMCI_INTMSK_ACD (1 << 14)
  63. #define DWMCI_INTMSK_EBE (1 << 15)
  64. /* Raw interrupt Regsiter */
  65. #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
  66. DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
  67. #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
  68. /* CTRL register */
  69. #define DWMCI_CTRL_RESET (1 << 0)
  70. #define DWMCI_CTRL_FIFO_RESET (1 << 1)
  71. #define DWMCI_CTRL_DMA_RESET (1 << 2)
  72. #define DWMCI_DMA_EN (1 << 5)
  73. #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
  74. #define DWMCI_IDMAC_EN (1 << 25)
  75. #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
  76. DWMCI_CTRL_DMA_RESET)
  77. /* CMD register */
  78. #define DWMCI_CMD_RESP_EXP (1 << 6)
  79. #define DWMCI_CMD_RESP_LENGTH (1 << 7)
  80. #define DWMCI_CMD_CHECK_CRC (1 << 8)
  81. #define DWMCI_CMD_DATA_EXP (1 << 9)
  82. #define DWMCI_CMD_RW (1 << 10)
  83. #define DWMCI_CMD_SEND_STOP (1 << 12)
  84. #define DWMCI_CMD_ABORT_STOP (1 << 14)
  85. #define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
  86. #define DWMCI_CMD_UPD_CLK (1 << 21)
  87. #define DWMCI_CMD_USE_HOLD_REG (1 << 29)
  88. #define DWMCI_CMD_START (1 << 31)
  89. /* CLKENA register */
  90. #define DWMCI_CLKEN_ENABLE (1 << 0)
  91. #define DWMCI_CLKEN_LOW_PWR (1 << 16)
  92. /* Card-type registe */
  93. #define DWMCI_CTYPE_1BIT 0
  94. #define DWMCI_CTYPE_4BIT (1 << 0)
  95. #define DWMCI_CTYPE_8BIT (1 << 16)
  96. /* Status Register */
  97. #define DWMCI_BUSY (1 << 9)
  98. #define DWMCI_FIFO_MASK 0x1fff
  99. #define DWMCI_FIFO_SHIFT 17
  100. /* FIFOTH Register */
  101. #define MSIZE(x) ((x) << 28)
  102. #define RX_WMARK(x) ((x) << 16)
  103. #define TX_WMARK(x) (x)
  104. #define RX_WMARK_SHIFT 16
  105. #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
  106. #define DWMCI_IDMAC_OWN (1 << 31)
  107. #define DWMCI_IDMAC_CH (1 << 4)
  108. #define DWMCI_IDMAC_FS (1 << 3)
  109. #define DWMCI_IDMAC_LD (1 << 2)
  110. /* Bus Mode Register */
  111. #define DWMCI_BMOD_IDMAC_RESET (1 << 0)
  112. #define DWMCI_BMOD_IDMAC_FB (1 << 1)
  113. #define DWMCI_BMOD_IDMAC_EN (1 << 7)
  114. /* UHS register */
  115. #define DWMCI_DDR_MODE (1 << 16)
  116. /* quirks */
  117. #define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
  118. /**
  119. * struct dwmci_host - Information about a designware MMC host
  120. *
  121. * @name: Device name
  122. * @ioaddr: Base I/O address of controller
  123. * @quirks: Quick flags - see DWMCI_QUIRK_...
  124. * @caps: Capabilities - see MMC_MODE_...
  125. * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
  126. * @div: Arbitrary clock divider value for use by controller
  127. * @dev_index: Arbitrary device index for use by controller
  128. * @dev_id: Arbitrary device ID for use by controller
  129. * @buswidth: Bus width in bits (8 or 4)
  130. * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
  131. * @mmc: Pointer to generic MMC structure for this device
  132. * @priv: Private pointer for use by controller
  133. */
  134. struct dwmci_host {
  135. const char *name;
  136. void *ioaddr;
  137. unsigned int quirks;
  138. unsigned int caps;
  139. unsigned int version;
  140. unsigned int clock;
  141. unsigned int bus_hz;
  142. unsigned int div;
  143. int dev_index;
  144. int dev_id;
  145. int buswidth;
  146. u32 fifoth_val;
  147. struct mmc *mmc;
  148. void *priv;
  149. void (*clksel)(struct dwmci_host *host);
  150. void (*board_init)(struct dwmci_host *host);
  151. /**
  152. * Get / set a particular MMC clock frequency
  153. *
  154. * This is used to request the current clock frequency of the clock
  155. * that drives the DWMMC peripheral. The caller will then use this
  156. * information to work out the divider it needs to achieve the
  157. * required MMC bus clock frequency. If you want to handle the
  158. * clock external to DWMMC, use @freq to select the frequency and
  159. * return that value too. Then DWMMC will put itself in bypass mode.
  160. *
  161. * @host: DWMMC host
  162. * @freq: Frequency the host is trying to achieve
  163. */
  164. unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
  165. #ifndef CONFIG_BLK
  166. struct mmc_config cfg;
  167. #endif
  168. /* use fifo mode to read and write data */
  169. bool fifo_mode;
  170. };
  171. struct dwmci_idmac {
  172. u32 flags;
  173. u32 cnt;
  174. u32 addr;
  175. u32 next_addr;
  176. } __aligned(ARCH_DMA_MINALIGN);
  177. static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
  178. {
  179. writel(val, host->ioaddr + reg);
  180. }
  181. static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
  182. {
  183. writew(val, host->ioaddr + reg);
  184. }
  185. static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
  186. {
  187. writeb(val, host->ioaddr + reg);
  188. }
  189. static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
  190. {
  191. return readl(host->ioaddr + reg);
  192. }
  193. static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
  194. {
  195. return readw(host->ioaddr + reg);
  196. }
  197. static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
  198. {
  199. return readb(host->ioaddr + reg);
  200. }
  201. #ifdef CONFIG_BLK
  202. /**
  203. * dwmci_setup_cfg() - Set up the configuration for DWMMC
  204. *
  205. * This is used to set up a DWMMC device when you are using CONFIG_BLK.
  206. *
  207. * This should be called from your MMC driver's probe() method once you have
  208. * the information required.
  209. *
  210. * Generally your driver will have a platform data structure which holds both
  211. * the configuration (struct mmc_config) and the MMC device info (struct mmc).
  212. * For example:
  213. *
  214. * struct rockchip_mmc_plat {
  215. * struct mmc_config cfg;
  216. * struct mmc mmc;
  217. * };
  218. *
  219. * ...
  220. *
  221. * Inside U_BOOT_DRIVER():
  222. * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
  223. *
  224. * To access platform data:
  225. * struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
  226. *
  227. * See rockchip_dw_mmc.c for an example.
  228. *
  229. * @cfg: Configuration structure to fill in (generally &plat->mmc)
  230. * @host: DWMMC host
  231. * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
  232. * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
  233. */
  234. void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
  235. u32 max_clk, u32 min_clk);
  236. /**
  237. * dwmci_bind() - Set up a new MMC block device
  238. *
  239. * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
  240. * It should be called from your driver's bind() method.
  241. *
  242. * See rockchip_dw_mmc.c for an example.
  243. *
  244. * @dev: Device to set up
  245. * @mmc: Pointer to mmc structure (normally &plat->mmc)
  246. * @cfg: Empty configuration structure (generally &plat->cfg). This is
  247. * normally all zeroes at this point. The only purpose of passing
  248. * this in is to set mmc->cfg to it.
  249. * @return 0 if OK, -ve if the block device could not be created
  250. */
  251. int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  252. #else
  253. /**
  254. * add_dwmci() - Add a new DWMMC interface
  255. *
  256. * This is used when you are not using CONFIG_BLK. Convert your driver over!
  257. *
  258. * @host: DWMMC host structure
  259. * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
  260. * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
  261. * @return 0 if OK, -ve on error
  262. */
  263. int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
  264. #endif /* !CONFIG_BLK */
  265. #ifdef CONFIG_DM_MMC
  266. /* Export the operations to drivers */
  267. int dwmci_probe(struct udevice *dev);
  268. extern const struct dm_mmc_ops dm_dwmci_ops;
  269. #endif
  270. #endif /* __DWMMC_HW_H */