board.c 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <fdtdec.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <dm/device.h>
  16. #include <dm/uclass.h>
  17. #include <versalpl.h>
  18. #include <linux/sizes.h>
  19. #include "../common/board.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #if defined(CONFIG_FPGA_VERSALPL)
  22. static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  23. #endif
  24. int board_init(void)
  25. {
  26. printf("EL Level:\tEL%d\n", current_el());
  27. #if defined(CONFIG_FPGA_VERSALPL)
  28. fpga_init();
  29. fpga_add(fpga_xilinx, &versalpl);
  30. #endif
  31. return 0;
  32. }
  33. int board_early_init_r(void)
  34. {
  35. u32 val;
  36. if (current_el() != 3)
  37. return 0;
  38. debug("iou_switch ctrl div0 %x\n",
  39. readl(&crlapb_base->iou_switch_ctrl));
  40. writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  41. (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  42. &crlapb_base->iou_switch_ctrl);
  43. /* Global timer init - Program time stamp reference clk */
  44. val = readl(&crlapb_base->timestamp_ref_ctrl);
  45. val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  46. writel(val, &crlapb_base->timestamp_ref_ctrl);
  47. debug("ref ctrl 0x%x\n",
  48. readl(&crlapb_base->timestamp_ref_ctrl));
  49. /* Clear reset of timestamp reg */
  50. writel(0, &crlapb_base->rst_timestamp);
  51. /*
  52. * Program freq register in System counter and
  53. * enable system counter.
  54. */
  55. writel(COUNTER_FREQUENCY,
  56. &iou_scntr_secure->base_frequency_id_register);
  57. debug("counter val 0x%x\n",
  58. readl(&iou_scntr_secure->base_frequency_id_register));
  59. writel(IOU_SCNTRS_CONTROL_EN,
  60. &iou_scntr_secure->counter_control_register);
  61. debug("scntrs control 0x%x\n",
  62. readl(&iou_scntr_secure->counter_control_register));
  63. debug("timer 0x%llx\n", get_ticks());
  64. debug("timer 0x%llx\n", get_ticks());
  65. return 0;
  66. }
  67. int board_late_init(void)
  68. {
  69. u32 reg = 0;
  70. u8 bootmode;
  71. struct udevice *dev;
  72. int bootseq = -1;
  73. int bootseq_len = 0;
  74. int env_targets_len = 0;
  75. const char *mode;
  76. char *new_targets;
  77. char *env_targets;
  78. ulong initrd_hi;
  79. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  80. debug("Saved variables - Skipping\n");
  81. return 0;
  82. }
  83. reg = readl(&crp_base->boot_mode_usr);
  84. if (reg >> BOOT_MODE_ALT_SHIFT)
  85. reg >>= BOOT_MODE_ALT_SHIFT;
  86. bootmode = reg & BOOT_MODES_MASK;
  87. puts("Bootmode: ");
  88. switch (bootmode) {
  89. case USB_MODE:
  90. puts("USB_MODE\n");
  91. mode = "dfu_usb";
  92. break;
  93. case JTAG_MODE:
  94. puts("JTAG_MODE\n");
  95. mode = "jtag pxe dhcp";
  96. break;
  97. case QSPI_MODE_24BIT:
  98. puts("QSPI_MODE_24\n");
  99. mode = "xspi0";
  100. break;
  101. case QSPI_MODE_32BIT:
  102. puts("QSPI_MODE_32\n");
  103. mode = "xspi0";
  104. break;
  105. case OSPI_MODE:
  106. puts("OSPI_MODE\n");
  107. mode = "xspi0";
  108. break;
  109. case EMMC_MODE:
  110. puts("EMMC_MODE\n");
  111. if (uclass_get_device_by_name(UCLASS_MMC,
  112. "sdhci@f1050000", &dev)) {
  113. puts("Boot from EMMC but without SD1 enabled!\n");
  114. return -1;
  115. }
  116. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  117. mode = "mmc";
  118. bootseq = dev->seq;
  119. break;
  120. case SD_MODE:
  121. puts("SD_MODE\n");
  122. if (uclass_get_device_by_name(UCLASS_MMC,
  123. "sdhci@f1040000", &dev)) {
  124. puts("Boot from SD0 but without SD0 enabled!\n");
  125. return -1;
  126. }
  127. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  128. mode = "mmc";
  129. bootseq = dev->seq;
  130. break;
  131. case SD1_LSHFT_MODE:
  132. puts("LVL_SHFT_");
  133. /* fall through */
  134. case SD_MODE1:
  135. puts("SD_MODE1\n");
  136. if (uclass_get_device_by_name(UCLASS_MMC,
  137. "sdhci@f1050000", &dev)) {
  138. puts("Boot from SD1 but without SD1 enabled!\n");
  139. return -1;
  140. }
  141. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  142. mode = "mmc";
  143. bootseq = dev->seq;
  144. break;
  145. default:
  146. mode = "";
  147. printf("Invalid Boot Mode:0x%x\n", bootmode);
  148. break;
  149. }
  150. if (bootseq >= 0) {
  151. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  152. debug("Bootseq len: %x\n", bootseq_len);
  153. }
  154. /*
  155. * One terminating char + one byte for space between mode
  156. * and default boot_targets
  157. */
  158. env_targets = env_get("boot_targets");
  159. if (env_targets)
  160. env_targets_len = strlen(env_targets);
  161. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  162. bootseq_len);
  163. if (!new_targets)
  164. return -ENOMEM;
  165. if (bootseq >= 0)
  166. sprintf(new_targets, "%s%x %s", mode, bootseq,
  167. env_targets ? env_targets : "");
  168. else
  169. sprintf(new_targets, "%s %s", mode,
  170. env_targets ? env_targets : "");
  171. env_set("boot_targets", new_targets);
  172. initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
  173. initrd_hi = round_down(initrd_hi, SZ_16M);
  174. env_set_addr("initrd_high", (void *)initrd_hi);
  175. return board_late_init_xilinx();
  176. }
  177. int dram_init_banksize(void)
  178. {
  179. int ret;
  180. ret = fdtdec_setup_memory_banksize();
  181. if (ret)
  182. return ret;
  183. mem_map_fill();
  184. return 0;
  185. }
  186. int dram_init(void)
  187. {
  188. if (fdtdec_setup_mem_size_base() != 0)
  189. return -EINVAL;
  190. return 0;
  191. }
  192. void reset_cpu(ulong addr)
  193. {
  194. }