ve8313.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. *
  7. * (C) Copyright 2010
  8. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  9. */
  10. #include <common.h>
  11. #include <fdt_support.h>
  12. #include <init.h>
  13. #include <linux/libfdt.h>
  14. #include <pci.h>
  15. #include <mpc83xx.h>
  16. #include <ns16550.h>
  17. #include <nand.h>
  18. #include <asm/bitops.h>
  19. #include <asm/io.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. extern void disable_addr_trans (void);
  22. extern void enable_addr_trans (void);
  23. int checkboard(void)
  24. {
  25. puts("Board: ve8313\n");
  26. return 0;
  27. }
  28. static long fixed_sdram(void)
  29. {
  30. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  31. #ifndef CONFIG_SYS_RAMBOOT
  32. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  33. u32 msize_log2 = __ilog2(msize);
  34. out_be32(&im->sysconf.ddrlaw[0].bar,
  35. (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
  36. out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
  37. out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  38. /*
  39. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  40. * or the DDR2 controller may fail to initialize correctly.
  41. */
  42. __udelay(50000);
  43. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  44. #warning Chip select bounds is only configurable in 16MB increments
  45. #endif
  46. out_be32(&im->ddr.csbnds[0].csbnds,
  47. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  48. (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
  49. CSBNDS_EA));
  50. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  51. /* Currently we use only one CS, so disable the other bank. */
  52. out_be32(&im->ddr.cs_config[1], 0);
  53. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  54. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  55. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  56. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  57. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  58. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
  59. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
  60. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  61. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
  62. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  63. sync();
  64. /* enable DDR controller */
  65. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  66. /* now check the real size */
  67. disable_addr_trans ();
  68. msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize);
  69. enable_addr_trans ();
  70. #endif
  71. return msize;
  72. }
  73. int dram_init(void)
  74. {
  75. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  76. volatile fsl_lbc_t *lbc = &im->im_lbc;
  77. u32 msize;
  78. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  79. return -1;
  80. /* DDR SDRAM - Main SODIMM */
  81. msize = fixed_sdram();
  82. /* Local Bus setup lbcr and mrtpr */
  83. out_be32(&lbc->lbcr, 0x00040000);
  84. out_be32(&lbc->mrtpr, 0x20000000);
  85. sync();
  86. /* return total bus SDRAM size(bytes) -- DDR */
  87. gd->ram_size = msize;
  88. return 0;
  89. }
  90. #define VE8313_WDT_EN 0x00020000
  91. #define VE8313_WDT_TRIG 0x00040000
  92. int board_early_init_f (void)
  93. {
  94. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  95. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
  96. #if defined(CONFIG_HW_WATCHDOG)
  97. /* enable WDT */
  98. clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
  99. #else
  100. /* disable WDT */
  101. setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
  102. #endif
  103. /* set WDT pins as output */
  104. setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
  105. return 0;
  106. }
  107. #if defined(CONFIG_HW_WATCHDOG)
  108. void hw_watchdog_reset(void)
  109. {
  110. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  111. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
  112. unsigned long reg;
  113. reg = in_be32(&gpio->dat);
  114. if (reg & VE8313_WDT_TRIG)
  115. clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
  116. else
  117. setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
  118. }
  119. #endif
  120. #if defined(CONFIG_PCI)
  121. static struct pci_region pci_regions[] = {
  122. {
  123. bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  124. phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  125. size: CONFIG_SYS_PCI1_MEM_SIZE,
  126. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  127. },
  128. {
  129. bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  130. phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  131. size: CONFIG_SYS_PCI1_MMIO_SIZE,
  132. flags: PCI_REGION_MEM
  133. },
  134. {
  135. bus_start: CONFIG_SYS_PCI1_IO_BASE,
  136. phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  137. size: CONFIG_SYS_PCI1_IO_SIZE,
  138. flags: PCI_REGION_IO
  139. }
  140. };
  141. void pci_init_board(void)
  142. {
  143. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  144. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  145. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  146. struct pci_region *reg[] = { pci_regions };
  147. /* Enable all 3 PCI_CLK_OUTPUTs. */
  148. setbits_be32(&clk->occr, 0xe0000000);
  149. /*
  150. * Configure PCI Local Access Windows
  151. */
  152. out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
  153. out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  154. out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
  155. out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
  156. mpc83xx_pci_init(1, reg);
  157. }
  158. #endif
  159. #if defined(CONFIG_OF_BOARD_SETUP)
  160. int ft_board_setup(void *blob, bd_t *bd)
  161. {
  162. ft_cpu_setup(blob, bd);
  163. #ifdef CONFIG_PCI
  164. ft_pci_setup(blob, bd);
  165. #endif
  166. return 0;
  167. }
  168. #endif