tqm834x.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2005
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <fdt_support.h>
  8. #include <ioports.h>
  9. #include <mpc83xx.h>
  10. #include <asm/mpc8349_pci.h>
  11. #include <i2c.h>
  12. #include <miiphy.h>
  13. #include <asm/mmu.h>
  14. #include <pci.h>
  15. #include <flash.h>
  16. #include <mtd/cfi_flash.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #define IOSYNC asm("eieio")
  19. #define ISYNC asm("isync")
  20. #define SYNC asm("sync")
  21. #define FPW FLASH_PORT_WIDTH
  22. #define FPWV FLASH_PORT_WIDTHV
  23. #define DDR_MAX_SIZE_PER_CS 0x20000000
  24. #if defined(DDR_CASLAT_20)
  25. #define TIMING_CASLAT TIMING_CFG1_CASLAT_20
  26. #define MODE_CASLAT DDR_MODE_CASLAT_20
  27. #else
  28. #define TIMING_CASLAT TIMING_CFG1_CASLAT_25
  29. #define MODE_CASLAT DDR_MODE_CASLAT_25
  30. #endif
  31. #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
  32. CSCONFIG_COL_BIT_9)
  33. /* External definitions */
  34. ulong flash_get_size (ulong base, int banknum);
  35. /* Local functions */
  36. static int detect_num_flash_banks(void);
  37. static long int get_ddr_bank_size(short cs, long *base);
  38. static void set_cs_bounds(short cs, ulong base, ulong size);
  39. static void set_cs_config(short cs, long config);
  40. static void set_ddr_config(void);
  41. /* Local variable */
  42. static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  43. /**************************************************************************
  44. * Board initialzation after relocation to RAM. Used to detect the number
  45. * of Flash banks on TQM834x.
  46. */
  47. int board_early_init_r (void) {
  48. /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
  49. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  50. return 0;
  51. /* detect the number of Flash banks */
  52. return detect_num_flash_banks();
  53. }
  54. /**************************************************************************
  55. * DRAM initalization and size detection
  56. */
  57. int dram_init(void)
  58. {
  59. long bank_size;
  60. long size;
  61. int cs;
  62. /* during size detection, set up the max DDRLAW size */
  63. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
  64. im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
  65. /* set CS bounds to maximum size */
  66. for(cs = 0; cs < 4; ++cs) {
  67. set_cs_bounds(cs,
  68. CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
  69. DDR_MAX_SIZE_PER_CS);
  70. set_cs_config(cs, INITIAL_CS_CONFIG);
  71. }
  72. /* configure ddr controller */
  73. set_ddr_config();
  74. udelay(200);
  75. /* enable DDR controller */
  76. im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
  77. SDRAM_CFG_SREN |
  78. SDRAM_CFG_SDRAM_TYPE_DDR1);
  79. SYNC;
  80. /* size detection */
  81. debug("\n");
  82. size = 0;
  83. for(cs = 0; cs < 4; ++cs) {
  84. debug("\nDetecting Bank%d\n", cs);
  85. bank_size = get_ddr_bank_size(cs,
  86. (long *)(CONFIG_SYS_SDRAM_BASE + size));
  87. size += bank_size;
  88. debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
  89. /* exit if less than one bank */
  90. if(size < DDR_MAX_SIZE_PER_CS) break;
  91. }
  92. gd->ram_size = size;
  93. return 0;
  94. }
  95. /**************************************************************************
  96. * checkboard()
  97. */
  98. int checkboard (void)
  99. {
  100. puts("Board: TQM834x\n");
  101. #ifdef CONFIG_PCI
  102. volatile immap_t * immr;
  103. u32 w, f;
  104. immr = (immap_t *)CONFIG_SYS_IMMR;
  105. if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
  106. printf("PCI: NOT in host mode..?!\n");
  107. return 0;
  108. }
  109. /* get bus width */
  110. w = 32;
  111. if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
  112. w = 64;
  113. /* get clock */
  114. f = gd->pci_clk;
  115. printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
  116. #else
  117. printf("PCI: disabled\n");
  118. #endif
  119. return 0;
  120. }
  121. /**************************************************************************
  122. *
  123. * Local functions
  124. *
  125. *************************************************************************/
  126. /**************************************************************************
  127. * Detect the number of flash banks (1 or 2). Store it in
  128. * a global variable tqm834x_num_flash_banks.
  129. * Bank detection code based on the Monitor code.
  130. */
  131. static int detect_num_flash_banks(void)
  132. {
  133. typedef unsigned long FLASH_PORT_WIDTH;
  134. typedef volatile unsigned long FLASH_PORT_WIDTHV;
  135. FPWV *bank1_base;
  136. FPWV *bank2_base;
  137. FPW bank1_read;
  138. FPW bank2_read;
  139. ulong bank1_size;
  140. ulong bank2_size;
  141. ulong total_size;
  142. cfi_flash_num_flash_banks = 2; /* assume two banks */
  143. /* Get bank 1 and 2 information */
  144. bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
  145. debug("Bank1 size: %lu\n", bank1_size);
  146. bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
  147. debug("Bank2 size: %lu\n", bank2_size);
  148. total_size = bank1_size + bank2_size;
  149. if (bank2_size > 0) {
  150. /* Seems like we've got bank 2, but maybe it's mirrored 1 */
  151. /* Set the base addresses */
  152. bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
  153. bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
  154. /* Put bank 2 into CFI command mode and read */
  155. bank2_base[0x55] = 0x00980098;
  156. IOSYNC;
  157. ISYNC;
  158. bank2_read = bank2_base[0x10];
  159. /* Read from bank 1 (it's in read mode) */
  160. bank1_read = bank1_base[0x10];
  161. /* Reset Flash */
  162. bank1_base[0] = 0x00F000F0;
  163. bank2_base[0] = 0x00F000F0;
  164. if (bank2_read == bank1_read) {
  165. /*
  166. * Looks like just one bank, but not sure yet. Let's
  167. * read from bank 2 in autosoelect mode.
  168. */
  169. bank2_base[0x0555] = 0x00AA00AA;
  170. bank2_base[0x02AA] = 0x00550055;
  171. bank2_base[0x0555] = 0x00900090;
  172. IOSYNC;
  173. ISYNC;
  174. bank2_read = bank2_base[0x10];
  175. /* Read from bank 1 (it's in read mode) */
  176. bank1_read = bank1_base[0x10];
  177. /* Reset Flash */
  178. bank1_base[0] = 0x00F000F0;
  179. bank2_base[0] = 0x00F000F0;
  180. if (bank2_read == bank1_read) {
  181. /*
  182. * In both CFI command and autoselect modes,
  183. * we got the some data reading from Flash.
  184. * There is only one mirrored bank.
  185. */
  186. cfi_flash_num_flash_banks = 1;
  187. total_size = bank1_size;
  188. }
  189. }
  190. }
  191. debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
  192. /* set OR0 and BR0 */
  193. set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
  194. OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
  195. set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
  196. (BR_MS_GPCM | BR_PS_32 | BR_V));
  197. return (0);
  198. }
  199. /*************************************************************************
  200. * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
  201. */
  202. static long int get_ddr_bank_size(short cs, long *base)
  203. {
  204. /* This array lists all valid DDR SDRAM configurations, with
  205. * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
  206. * The last entry has to to have size equal 0 and is igonred during
  207. * autodection. Bank sizes must be in increasing order of size
  208. */
  209. struct {
  210. long row;
  211. long col;
  212. long size;
  213. } conf[] = {
  214. {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
  215. {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
  216. {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
  217. {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
  218. {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
  219. {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
  220. {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
  221. {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
  222. {0, 0, 0}
  223. };
  224. int i;
  225. int detected;
  226. long size;
  227. detected = -1;
  228. for(i = 0; conf[i].size != 0; ++i) {
  229. /* set sdram bank configuration */
  230. set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
  231. debug("Getting RAM size...\n");
  232. size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
  233. if((size == conf[i].size) && (i == detected + 1))
  234. detected = i;
  235. debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
  236. conf[i].row,
  237. conf[i].col,
  238. conf[i].size >> 20,
  239. base,
  240. size >> 20);
  241. }
  242. if(detected == -1){
  243. /* disable empty cs */
  244. debug("\nNo valid configurations for CS%d, disabling...\n", cs);
  245. set_cs_config(cs, 0);
  246. return 0;
  247. }
  248. debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
  249. conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
  250. /* configure cs ro detected params */
  251. set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
  252. conf[detected].col);
  253. set_cs_bounds(cs, (long)base, conf[detected].size);
  254. return(conf[detected].size);
  255. }
  256. /**************************************************************************
  257. * Sets DDR bank CS bounds.
  258. */
  259. static void set_cs_bounds(short cs, ulong base, ulong size)
  260. {
  261. debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
  262. if(size == 0){
  263. im->ddr.csbnds[cs].csbnds = 0x00000000;
  264. } else {
  265. im->ddr.csbnds[cs].csbnds =
  266. ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  267. (((base + size - 1) >> CSBNDS_EA_SHIFT) &
  268. CSBNDS_EA);
  269. }
  270. SYNC;
  271. }
  272. /**************************************************************************
  273. * Sets DDR banks CS configuration.
  274. * config == 0x00000000 disables the CS.
  275. */
  276. static void set_cs_config(short cs, long config)
  277. {
  278. debug("Setting config %08lx for cs %d\n", config, cs);
  279. im->ddr.cs_config[cs] = config;
  280. SYNC;
  281. }
  282. /**************************************************************************
  283. * Sets DDR clocks, timings and configuration.
  284. */
  285. static void set_ddr_config(void) {
  286. /* clock control */
  287. im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
  288. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
  289. SYNC;
  290. /* timing configuration */
  291. im->ddr.timing_cfg_1 =
  292. (4 << TIMING_CFG1_PRETOACT_SHIFT) |
  293. (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
  294. (4 << TIMING_CFG1_ACTTORW_SHIFT) |
  295. (5 << TIMING_CFG1_REFREC_SHIFT) |
  296. (3 << TIMING_CFG1_WRREC_SHIFT) |
  297. (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
  298. (1 << TIMING_CFG1_WRTORD_SHIFT) |
  299. (TIMING_CFG1_CASLAT & TIMING_CASLAT);
  300. im->ddr.timing_cfg_2 =
  301. TIMING_CFG2_CPO_DEF |
  302. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
  303. SYNC;
  304. /* don't enable DDR controller yet */
  305. im->ddr.sdram_cfg =
  306. SDRAM_CFG_SREN |
  307. SDRAM_CFG_SDRAM_TYPE_DDR1;
  308. SYNC;
  309. /* Set SDRAM mode */
  310. im->ddr.sdram_mode =
  311. ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
  312. SDRAM_MODE_ESD_SHIFT) |
  313. ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
  314. SDRAM_MODE_SD_SHIFT) |
  315. ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
  316. MODE_CASLAT);
  317. SYNC;
  318. /* Set fast SDRAM refresh rate */
  319. im->ddr.sdram_interval =
  320. (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
  321. (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
  322. SYNC;
  323. /* Workaround for DDR6 Erratum
  324. * see MPC8349E Device Errata Rev.8, 2/2006
  325. * This workaround influences the MPC internal "input enables"
  326. * dependent on CAS latency and MPC revision. According to errata
  327. * sheet the internal reserved registers for this workaround are
  328. * not available from revision 2.0 and up.
  329. */
  330. /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
  331. * (0x200)
  332. */
  333. if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
  334. /* There is a internal reserved register at IMMRBAR+0x2F00
  335. * which has to be written with a certain value defined by
  336. * errata sheet.
  337. */
  338. u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
  339. #if defined(DDR_CASLAT_20)
  340. *reserved_p = 0x201c0000;
  341. #else
  342. *reserved_p = 0x202c0000;
  343. #endif
  344. }
  345. }
  346. #ifdef CONFIG_OF_BOARD_SETUP
  347. int ft_board_setup(void *blob, bd_t *bd)
  348. {
  349. ft_cpu_setup(blob, bd);
  350. #ifdef CONFIG_PCI
  351. ft_pci_setup(blob, bd);
  352. #endif /* CONFIG_PCI */
  353. return 0;
  354. }
  355. #endif /* CONFIG_OF_BOARD_SETUP */