evm.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Texas Instruments Incorporated, <www.ti.com>
  5. *
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. *
  8. * Based on previous work by:
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <fdt_support.h>
  15. #include <init.h>
  16. #include <palmas.h>
  17. #include <sata.h>
  18. #include <serial.h>
  19. #include <linux/string.h>
  20. #include <asm/gpio.h>
  21. #include <usb.h>
  22. #include <linux/usb/gadget.h>
  23. #include <asm/omap_common.h>
  24. #include <asm/omap_sec_common.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/dra7xx_iodelay.h>
  27. #include <asm/emif.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <asm/arch/mmc_host_def.h>
  30. #include <asm/arch/sata.h>
  31. #include <dwc3-uboot.h>
  32. #include <dwc3-omap-uboot.h>
  33. #include <i2c.h>
  34. #include <ti-usb-phy-uboot.h>
  35. #include <miiphy.h>
  36. #include "mux_data.h"
  37. #include "../common/board_detect.h"
  38. #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
  39. #define board_is_dra74x_evm() board_ti_is("5777xCPU")
  40. #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
  41. #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
  42. #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
  43. (strncmp("H", board_ti_get_rev(), 1) <= 0))
  44. #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
  45. (strncmp("C", board_ti_get_rev(), 1) <= 0))
  46. #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
  47. board_ti_get_emif2_size()
  48. #ifdef CONFIG_DRIVER_TI_CPSW
  49. #include <cpsw.h>
  50. #endif
  51. DECLARE_GLOBAL_DATA_PTR;
  52. /* GPIO 7_11 */
  53. #define GPIO_DDR_VTT_EN 203
  54. #define SYSINFO_BOARD_NAME_MAX_LEN 37
  55. /* I2C I/O Expander */
  56. #define NAND_PCF8575_ADDR 0x21
  57. #define NAND_PCF8575_I2C_BUS_NUM 0
  58. const struct omap_sysinfo sysinfo = {
  59. "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  60. };
  61. static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  62. .sdram_config_init = 0x61851ab2,
  63. .sdram_config = 0x61851ab2,
  64. .sdram_config2 = 0x08000000,
  65. .ref_ctrl = 0x000040F1,
  66. .ref_ctrl_final = 0x00001035,
  67. .sdram_tim1 = 0xCCCF36B3,
  68. .sdram_tim2 = 0x308F7FDA,
  69. .sdram_tim3 = 0x427F88A8,
  70. .read_idle_ctrl = 0x00050000,
  71. .zq_config = 0x0007190B,
  72. .temp_alert_config = 0x00000000,
  73. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  74. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  75. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  76. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  77. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  78. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  79. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  80. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  81. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  82. .emif_rd_wr_lvl_ctl = 0x00000000,
  83. .emif_rd_wr_exec_thresh = 0x00000305
  84. };
  85. static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  86. .sdram_config_init = 0x61851B32,
  87. .sdram_config = 0x61851B32,
  88. .sdram_config2 = 0x08000000,
  89. .ref_ctrl = 0x000040F1,
  90. .ref_ctrl_final = 0x00001035,
  91. .sdram_tim1 = 0xCCCF36B3,
  92. .sdram_tim2 = 0x308F7FDA,
  93. .sdram_tim3 = 0x427F88A8,
  94. .read_idle_ctrl = 0x00050000,
  95. .zq_config = 0x0007190B,
  96. .temp_alert_config = 0x00000000,
  97. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  98. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  99. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  100. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  101. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  102. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  103. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  104. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  105. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  106. .emif_rd_wr_lvl_ctl = 0x00000000,
  107. .emif_rd_wr_exec_thresh = 0x00000305
  108. };
  109. static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
  110. .sdram_config_init = 0x61862B32,
  111. .sdram_config = 0x61862B32,
  112. .sdram_config2 = 0x08000000,
  113. .ref_ctrl = 0x0000514C,
  114. .ref_ctrl_final = 0x0000144A,
  115. .sdram_tim1 = 0xD113781C,
  116. .sdram_tim2 = 0x30717FE3,
  117. .sdram_tim3 = 0x409F86A8,
  118. .read_idle_ctrl = 0x00050000,
  119. .zq_config = 0x5007190B,
  120. .temp_alert_config = 0x00000000,
  121. .emif_ddr_phy_ctlr_1_init = 0x0024400D,
  122. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  123. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  124. .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
  125. .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
  126. .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
  127. .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
  128. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  129. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  130. .emif_rd_wr_lvl_ctl = 0x00000000,
  131. .emif_rd_wr_exec_thresh = 0x00000305
  132. };
  133. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
  134. .sdram_config_init = 0x61862BB2,
  135. .sdram_config = 0x61862BB2,
  136. .sdram_config2 = 0x00000000,
  137. .ref_ctrl = 0x0000514D,
  138. .ref_ctrl_final = 0x0000144A,
  139. .sdram_tim1 = 0xD1137824,
  140. .sdram_tim2 = 0x30B37FE3,
  141. .sdram_tim3 = 0x409F8AD8,
  142. .read_idle_ctrl = 0x00050000,
  143. .zq_config = 0x5007190B,
  144. .temp_alert_config = 0x00000000,
  145. .emif_ddr_phy_ctlr_1_init = 0x0824400E,
  146. .emif_ddr_phy_ctlr_1 = 0x0E24400E,
  147. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  148. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  149. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  150. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  151. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  152. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  153. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  154. .emif_rd_wr_lvl_ctl = 0x00000000,
  155. .emif_rd_wr_exec_thresh = 0x00000305
  156. };
  157. const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
  158. .sdram_config_init = 0x61851ab2,
  159. .sdram_config = 0x61851ab2,
  160. .sdram_config2 = 0x08000000,
  161. .ref_ctrl = 0x000040F1,
  162. .ref_ctrl_final = 0x00001035,
  163. .sdram_tim1 = 0xCCCF36B3,
  164. .sdram_tim2 = 0x30BF7FDA,
  165. .sdram_tim3 = 0x427F8BA8,
  166. .read_idle_ctrl = 0x00050000,
  167. .zq_config = 0x0007190B,
  168. .temp_alert_config = 0x00000000,
  169. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  170. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  171. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  172. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  173. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  174. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  175. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  176. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  177. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  178. .emif_rd_wr_lvl_ctl = 0x00000000,
  179. .emif_rd_wr_exec_thresh = 0x00000305
  180. };
  181. const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
  182. .sdram_config_init = 0x61851B32,
  183. .sdram_config = 0x61851B32,
  184. .sdram_config2 = 0x08000000,
  185. .ref_ctrl = 0x000040F1,
  186. .ref_ctrl_final = 0x00001035,
  187. .sdram_tim1 = 0xCCCF36B3,
  188. .sdram_tim2 = 0x308F7FDA,
  189. .sdram_tim3 = 0x427F88A8,
  190. .read_idle_ctrl = 0x00050000,
  191. .zq_config = 0x0007190B,
  192. .temp_alert_config = 0x00000000,
  193. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  194. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  195. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  196. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  197. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  198. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  199. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  200. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  201. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  202. .emif_rd_wr_lvl_ctl = 0x00000000,
  203. .emif_rd_wr_exec_thresh = 0x00000305
  204. };
  205. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
  206. .sdram_config_init = 0x61862B32,
  207. .sdram_config = 0x61862B32,
  208. .sdram_config2 = 0x00000000,
  209. .ref_ctrl = 0x0000514C,
  210. .ref_ctrl_final = 0x0000144A,
  211. .sdram_tim1 = 0xD113783C,
  212. .sdram_tim2 = 0x30B47FE3,
  213. .sdram_tim3 = 0x409F8AD8,
  214. .read_idle_ctrl = 0x00050000,
  215. .zq_config = 0x5007190B,
  216. .temp_alert_config = 0x00000000,
  217. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  218. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  219. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  220. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  221. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  222. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  223. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  224. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  225. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  226. .emif_rd_wr_lvl_ctl = 0x00000000,
  227. .emif_rd_wr_exec_thresh = 0x00000305
  228. };
  229. const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
  230. .sdram_config_init = 0x61862B32,
  231. .sdram_config = 0x61862B32,
  232. .sdram_config2 = 0x00000000,
  233. .ref_ctrl = 0x0000514C,
  234. .ref_ctrl_final = 0x0000144A,
  235. .sdram_tim1 = 0xD113781C,
  236. .sdram_tim2 = 0x30B47FE3,
  237. .sdram_tim3 = 0x409F8AD8,
  238. .read_idle_ctrl = 0x00050000,
  239. .zq_config = 0x5007190B,
  240. .temp_alert_config = 0x00000000,
  241. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  242. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  243. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  244. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  245. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  246. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  247. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  248. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  249. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  250. .emif_rd_wr_lvl_ctl = 0x00000000,
  251. .emif_rd_wr_exec_thresh = 0x00000305
  252. };
  253. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  254. {
  255. u64 ram_size;
  256. ram_size = board_ti_get_emif_size();
  257. switch (omap_revision()) {
  258. case DRA752_ES1_0:
  259. case DRA752_ES1_1:
  260. case DRA752_ES2_0:
  261. switch (emif_nr) {
  262. case 1:
  263. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  264. *regs = &emif1_ddr3_532_mhz_1cs_2G;
  265. else
  266. *regs = &emif1_ddr3_532_mhz_1cs;
  267. break;
  268. case 2:
  269. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  270. *regs = &emif2_ddr3_532_mhz_1cs_2G;
  271. else
  272. *regs = &emif2_ddr3_532_mhz_1cs;
  273. break;
  274. }
  275. break;
  276. case DRA762_ABZ_ES1_0:
  277. case DRA762_ACD_ES1_0:
  278. case DRA762_ES1_0:
  279. if (emif_nr == 1)
  280. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
  281. else
  282. *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
  283. break;
  284. case DRA722_ES1_0:
  285. case DRA722_ES2_0:
  286. case DRA722_ES2_1:
  287. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  288. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
  289. else
  290. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
  291. break;
  292. default:
  293. *regs = &emif1_ddr3_532_mhz_1cs;
  294. }
  295. }
  296. static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
  297. .dmm_lisa_map_0 = 0x0,
  298. .dmm_lisa_map_1 = 0x80640300,
  299. .dmm_lisa_map_2 = 0xC0500220,
  300. .dmm_lisa_map_3 = 0xFF020100,
  301. .is_ma_present = 0x1
  302. };
  303. static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
  304. .dmm_lisa_map_0 = 0x0,
  305. .dmm_lisa_map_1 = 0x0,
  306. .dmm_lisa_map_2 = 0x80600100,
  307. .dmm_lisa_map_3 = 0xFF020100,
  308. .is_ma_present = 0x1
  309. };
  310. const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
  311. .dmm_lisa_map_0 = 0x0,
  312. .dmm_lisa_map_1 = 0x0,
  313. .dmm_lisa_map_2 = 0x80740300,
  314. .dmm_lisa_map_3 = 0xFF020100,
  315. .is_ma_present = 0x1
  316. };
  317. /*
  318. * DRA722 EVM EMIF1 2GB CONFIGURATION
  319. * EMIF1 4 devices of 512Mb x 8 Micron
  320. */
  321. const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
  322. .dmm_lisa_map_0 = 0x0,
  323. .dmm_lisa_map_1 = 0x0,
  324. .dmm_lisa_map_2 = 0x80700100,
  325. .dmm_lisa_map_3 = 0xFF020100,
  326. .is_ma_present = 0x1
  327. };
  328. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  329. {
  330. u64 ram_size;
  331. ram_size = board_ti_get_emif_size();
  332. switch (omap_revision()) {
  333. case DRA762_ABZ_ES1_0:
  334. case DRA762_ACD_ES1_0:
  335. case DRA762_ES1_0:
  336. case DRA752_ES1_0:
  337. case DRA752_ES1_1:
  338. case DRA752_ES2_0:
  339. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  340. *dmm_lisa_regs = &lisa_map_dra7_2GB;
  341. else
  342. *dmm_lisa_regs = &lisa_map_dra7_1536MB;
  343. break;
  344. case DRA722_ES1_0:
  345. case DRA722_ES2_0:
  346. case DRA722_ES2_1:
  347. default:
  348. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  349. *dmm_lisa_regs = &lisa_map_2G_x_2;
  350. else
  351. *dmm_lisa_regs = &lisa_map_2G_x_4;
  352. break;
  353. }
  354. }
  355. struct vcores_data dra752_volts = {
  356. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  357. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  358. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  359. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  360. .mpu.pmic = &tps659038,
  361. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  362. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  363. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  364. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  365. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  366. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  367. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  368. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  369. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  370. .eve.pmic = &tps659038,
  371. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  372. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  373. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  374. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  375. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  376. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  377. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  378. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  379. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  380. .gpu.pmic = &tps659038,
  381. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  382. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  383. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  384. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  385. .core.addr = TPS659038_REG_ADDR_SMPS7,
  386. .core.pmic = &tps659038,
  387. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  388. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  389. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  390. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  391. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  392. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  393. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  394. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  395. .iva.pmic = &tps659038,
  396. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  397. };
  398. struct vcores_data dra76x_volts = {
  399. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  400. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  401. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  402. .mpu.addr = LP87565_REG_ADDR_BUCK01,
  403. .mpu.pmic = &lp87565,
  404. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  405. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  406. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  407. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  408. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  409. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  410. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  411. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  412. .eve.addr = TPS65917_REG_ADDR_SMPS1,
  413. .eve.pmic = &tps659038,
  414. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  415. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  416. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  417. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  418. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  419. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  420. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  421. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  422. .gpu.addr = LP87565_REG_ADDR_BUCK23,
  423. .gpu.pmic = &lp87565,
  424. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  425. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  426. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  427. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  428. .core.addr = TPS65917_REG_ADDR_SMPS3,
  429. .core.pmic = &tps659038,
  430. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  431. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  432. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  433. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  434. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  435. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  436. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  437. .iva.addr = TPS65917_REG_ADDR_SMPS4,
  438. .iva.pmic = &tps659038,
  439. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  440. };
  441. struct vcores_data dra722_volts = {
  442. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  443. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  444. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  445. .mpu.addr = TPS65917_REG_ADDR_SMPS1,
  446. .mpu.pmic = &tps659038,
  447. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  448. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  449. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  450. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  451. .core.addr = TPS65917_REG_ADDR_SMPS2,
  452. .core.pmic = &tps659038,
  453. /*
  454. * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
  455. * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
  456. */
  457. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  458. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  459. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  460. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  461. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  462. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  463. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  464. .gpu.addr = TPS65917_REG_ADDR_SMPS3,
  465. .gpu.pmic = &tps659038,
  466. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  467. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  468. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  469. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  470. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  471. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  472. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  473. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  474. .eve.addr = TPS65917_REG_ADDR_SMPS3,
  475. .eve.pmic = &tps659038,
  476. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  477. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  478. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  479. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  480. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  481. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  482. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  483. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  484. .iva.addr = TPS65917_REG_ADDR_SMPS3,
  485. .iva.pmic = &tps659038,
  486. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  487. };
  488. struct vcores_data dra718_volts = {
  489. /*
  490. * In the case of dra71x GPU MPU and CORE
  491. * are all powered up by BUCK0 of LP873X PMIC
  492. */
  493. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  494. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  495. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  496. .mpu.addr = LP873X_REG_ADDR_BUCK0,
  497. .mpu.pmic = &lp8733,
  498. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  499. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  500. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  501. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  502. .core.addr = LP873X_REG_ADDR_BUCK0,
  503. .core.pmic = &lp8733,
  504. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  505. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  506. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  507. .gpu.addr = LP873X_REG_ADDR_BUCK0,
  508. .gpu.pmic = &lp8733,
  509. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  510. /*
  511. * The DSPEVE and IVA rails are grouped on DRA71x-evm
  512. * and are powered by BUCK1 of LP873X PMIC
  513. */
  514. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  515. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  516. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  517. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  518. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  519. .eve.addr = LP873X_REG_ADDR_BUCK1,
  520. .eve.pmic = &lp8733,
  521. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  522. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  523. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  524. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  525. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  526. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  527. .iva.addr = LP873X_REG_ADDR_BUCK1,
  528. .iva.pmic = &lp8733,
  529. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  530. };
  531. int get_voltrail_opp(int rail_offset)
  532. {
  533. int opp;
  534. switch (rail_offset) {
  535. case VOLT_MPU:
  536. opp = DRA7_MPU_OPP;
  537. /* DRA71x supports only OPP_NOM for MPU */
  538. if (board_is_dra71x_evm())
  539. opp = OPP_NOM;
  540. break;
  541. case VOLT_CORE:
  542. opp = DRA7_CORE_OPP;
  543. /* DRA71x supports only OPP_NOM for CORE */
  544. if (board_is_dra71x_evm())
  545. opp = OPP_NOM;
  546. break;
  547. case VOLT_GPU:
  548. opp = DRA7_GPU_OPP;
  549. /* DRA71x supports only OPP_NOM for GPU */
  550. if (board_is_dra71x_evm())
  551. opp = OPP_NOM;
  552. break;
  553. case VOLT_EVE:
  554. opp = DRA7_DSPEVE_OPP;
  555. /*
  556. * DRA71x does not support OPP_OD for EVE.
  557. * If OPP_OD is selected by menuconfig, fallback
  558. * to OPP_NOM.
  559. */
  560. if (board_is_dra71x_evm() && opp == OPP_OD)
  561. opp = OPP_NOM;
  562. break;
  563. case VOLT_IVA:
  564. opp = DRA7_IVA_OPP;
  565. /*
  566. * DRA71x does not support OPP_OD for IVA.
  567. * If OPP_OD is selected by menuconfig, fallback
  568. * to OPP_NOM.
  569. */
  570. if (board_is_dra71x_evm() && opp == OPP_OD)
  571. opp = OPP_NOM;
  572. break;
  573. default:
  574. opp = OPP_NOM;
  575. }
  576. return opp;
  577. }
  578. /**
  579. * @brief board_init
  580. *
  581. * @return 0
  582. */
  583. int board_init(void)
  584. {
  585. gpmc_init();
  586. gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  587. return 0;
  588. }
  589. int dram_init_banksize(void)
  590. {
  591. u64 ram_size;
  592. ram_size = board_ti_get_emif_size();
  593. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  594. gd->bd->bi_dram[0].size = get_effective_memsize();
  595. if (ram_size > CONFIG_MAX_MEM_MAPPED) {
  596. gd->bd->bi_dram[1].start = 0x200000000;
  597. gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
  598. }
  599. return 0;
  600. }
  601. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  602. static int device_okay(const char *path)
  603. {
  604. int node;
  605. node = fdt_path_offset(gd->fdt_blob, path);
  606. if (node < 0)
  607. return 0;
  608. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  609. }
  610. #endif
  611. int board_late_init(void)
  612. {
  613. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  614. char *name = "unknown";
  615. if (is_dra72x()) {
  616. if (board_is_dra72x_revc_or_later())
  617. name = "dra72x-revc";
  618. else if (board_is_dra71x_evm())
  619. name = "dra71x";
  620. else
  621. name = "dra72x";
  622. } else if (is_dra76x_abz()) {
  623. name = "dra76x_abz";
  624. } else if (is_dra76x_acd()) {
  625. name = "dra76x_acd";
  626. } else {
  627. name = "dra7xx";
  628. }
  629. set_board_info_env(name);
  630. /*
  631. * Default FIT boot on HS devices. Non FIT images are not allowed
  632. * on HS devices.
  633. */
  634. if (get_device_type() == HS_DEVICE)
  635. env_set("boot_fit", "1");
  636. omap_die_id_serial();
  637. omap_set_fastboot_vars();
  638. /*
  639. * Hook the LDO1 regulator to EN pin. This applies only to LP8733
  640. * Rest all regulators are hooked to EN Pin at reset.
  641. */
  642. if (board_is_dra71x_evm())
  643. palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
  644. #endif
  645. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  646. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  647. enable_usb_clocks(0);
  648. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  649. enable_usb_clocks(1);
  650. #endif
  651. return 0;
  652. }
  653. #ifdef CONFIG_SPL_BUILD
  654. void do_board_detect(void)
  655. {
  656. int rc;
  657. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  658. CONFIG_EEPROM_CHIP_ADDRESS);
  659. if (rc)
  660. printf("ti_i2c_eeprom_init failed %d\n", rc);
  661. }
  662. #else
  663. void do_board_detect(void)
  664. {
  665. char *bname = NULL;
  666. int rc;
  667. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  668. CONFIG_EEPROM_CHIP_ADDRESS);
  669. if (rc)
  670. printf("ti_i2c_eeprom_init failed %d\n", rc);
  671. if (board_is_dra74x_evm()) {
  672. bname = "DRA74x EVM";
  673. } else if (board_is_dra72x_evm()) {
  674. bname = "DRA72x EVM";
  675. } else if (board_is_dra71x_evm()) {
  676. bname = "DRA71x EVM";
  677. } else if (board_is_dra76x_evm()) {
  678. bname = "DRA76x EVM";
  679. } else {
  680. /* If EEPROM is not populated */
  681. if (is_dra72x())
  682. bname = "DRA72x EVM";
  683. else
  684. bname = "DRA74x EVM";
  685. }
  686. if (bname)
  687. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  688. "Board: %s REV %s\n", bname, board_ti_get_rev());
  689. }
  690. #endif /* CONFIG_SPL_BUILD */
  691. void vcores_init(void)
  692. {
  693. if (board_is_dra74x_evm()) {
  694. *omap_vcores = &dra752_volts;
  695. } else if (board_is_dra72x_evm()) {
  696. *omap_vcores = &dra722_volts;
  697. } else if (board_is_dra71x_evm()) {
  698. *omap_vcores = &dra718_volts;
  699. } else if (board_is_dra76x_evm()) {
  700. *omap_vcores = &dra76x_volts;
  701. } else {
  702. /* If EEPROM is not populated */
  703. if (is_dra72x())
  704. *omap_vcores = &dra722_volts;
  705. else
  706. *omap_vcores = &dra752_volts;
  707. }
  708. }
  709. void set_muxconf_regs(void)
  710. {
  711. do_set_mux32((*ctrl)->control_padconf_core_base,
  712. early_padconf, ARRAY_SIZE(early_padconf));
  713. }
  714. #if defined(CONFIG_MTD_RAW_NAND)
  715. static int nand_sw_detect(void)
  716. {
  717. int rc;
  718. uchar data[2];
  719. struct udevice *dev;
  720. rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
  721. NAND_PCF8575_ADDR, 0, &dev);
  722. if (rc)
  723. return -1;
  724. rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
  725. if (rc)
  726. return -1;
  727. /* We are only interested in P10 and P11 on PCF8575 which is equal to
  728. * bits 8 and 9.
  729. */
  730. data[1] = data[1] & 0x3;
  731. /* Ensure only P11 is set and P10 is cleared. This ensures only
  732. * NAND (P10) is configured and not NOR (P11) which are both low
  733. * true signals. NAND and NOR settings should not be enabled at
  734. * the same time.
  735. */
  736. if (data[1] == 0x2)
  737. return 0;
  738. return -1;
  739. }
  740. #else
  741. int nand_sw_detect(void)
  742. {
  743. return -1;
  744. }
  745. #endif
  746. #ifdef CONFIG_IODELAY_RECALIBRATION
  747. void recalibrate_iodelay(void)
  748. {
  749. struct pad_conf_entry const *pads, *delta_pads = NULL;
  750. struct iodelay_cfg_entry const *iodelay;
  751. int npads, niodelays, delta_npads = 0;
  752. int ret;
  753. switch (omap_revision()) {
  754. case DRA722_ES1_0:
  755. case DRA722_ES2_0:
  756. case DRA722_ES2_1:
  757. pads = dra72x_core_padconf_array_common;
  758. npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
  759. if (board_is_dra71x_evm()) {
  760. pads = dra71x_core_padconf_array;
  761. npads = ARRAY_SIZE(dra71x_core_padconf_array);
  762. iodelay = dra71_iodelay_cfg_array;
  763. niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
  764. /* If SW8 on the EVM is set to enable NAND then
  765. * overwrite the pins used by VOUT3 with NAND.
  766. */
  767. if (!nand_sw_detect()) {
  768. delta_pads = dra71x_nand_padconf_array;
  769. delta_npads =
  770. ARRAY_SIZE(dra71x_nand_padconf_array);
  771. } else {
  772. delta_pads = dra71x_vout3_padconf_array;
  773. delta_npads =
  774. ARRAY_SIZE(dra71x_vout3_padconf_array);
  775. }
  776. } else if (board_is_dra72x_revc_or_later()) {
  777. delta_pads = dra72x_rgmii_padconf_array_revc;
  778. delta_npads =
  779. ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
  780. iodelay = dra72_iodelay_cfg_array_revc;
  781. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
  782. } else {
  783. delta_pads = dra72x_rgmii_padconf_array_revb;
  784. delta_npads =
  785. ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
  786. iodelay = dra72_iodelay_cfg_array_revb;
  787. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
  788. }
  789. break;
  790. case DRA752_ES1_0:
  791. case DRA752_ES1_1:
  792. pads = dra74x_core_padconf_array;
  793. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  794. iodelay = dra742_es1_1_iodelay_cfg_array;
  795. niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  796. break;
  797. case DRA762_ACD_ES1_0:
  798. case DRA762_ES1_0:
  799. pads = dra76x_core_padconf_array;
  800. npads = ARRAY_SIZE(dra76x_core_padconf_array);
  801. iodelay = dra76x_es1_0_iodelay_cfg_array;
  802. niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
  803. break;
  804. default:
  805. case DRA752_ES2_0:
  806. case DRA762_ABZ_ES1_0:
  807. pads = dra74x_core_padconf_array;
  808. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  809. iodelay = dra742_es2_0_iodelay_cfg_array;
  810. niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  811. /* Setup port1 and port2 for rgmii with 'no-id' mode */
  812. clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
  813. RGMII1_ID_MODE_N_MASK);
  814. break;
  815. }
  816. /* Setup I/O isolation */
  817. ret = __recalibrate_iodelay_start();
  818. if (ret)
  819. goto err;
  820. /* Do the muxing here */
  821. do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
  822. /* Now do the weird minor deltas that should be safe */
  823. if (delta_npads)
  824. do_set_mux32((*ctrl)->control_padconf_core_base,
  825. delta_pads, delta_npads);
  826. if (is_dra76x())
  827. /* Set mux for MCAN instead of DCAN1 */
  828. clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
  829. MCAN_SEL_ALT_MASK, MCAN_SEL);
  830. /* Setup IOdelay configuration */
  831. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  832. err:
  833. /* Closeup.. remove isolation */
  834. __recalibrate_iodelay_end(ret);
  835. }
  836. #endif
  837. #if defined(CONFIG_MMC)
  838. int board_mmc_init(bd_t *bis)
  839. {
  840. omap_mmc_init(0, 0, 0, -1, -1);
  841. omap_mmc_init(1, 0, 0, -1, -1);
  842. return 0;
  843. }
  844. void board_mmc_poweron_ldo(uint voltage)
  845. {
  846. if (board_is_dra71x_evm()) {
  847. if (voltage == LDO_VOLT_3V0)
  848. voltage = 0x19;
  849. else if (voltage == LDO_VOLT_1V8)
  850. voltage = 0xa;
  851. lp873x_mmc1_poweron_ldo(voltage);
  852. } else if (board_is_dra76x_evm()) {
  853. palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
  854. } else {
  855. palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
  856. }
  857. }
  858. static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
  859. .hw_rev = "rev11",
  860. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  861. MMC_CAP(UHS_SDR104),
  862. .max_freq = 96000000,
  863. };
  864. static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
  865. .hw_rev = "rev11",
  866. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  867. MMC_CAP(UHS_SDR104) |
  868. MMC_CAP(UHS_SDR50),
  869. .max_freq = 48000000,
  870. };
  871. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  872. {
  873. switch (omap_revision()) {
  874. case DRA752_ES1_0:
  875. case DRA752_ES1_1:
  876. if (addr == OMAP_HSMMC1_BASE)
  877. return &dra7x_es1_1_mmc1_fixups;
  878. else
  879. return &dra7x_es1_1_mmc23_fixups;
  880. default:
  881. return NULL;
  882. }
  883. }
  884. #endif
  885. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  886. int spl_start_uboot(void)
  887. {
  888. /* break into full u-boot on 'c' */
  889. if (serial_tstc() && serial_getc() == 'c')
  890. return 1;
  891. #ifdef CONFIG_SPL_ENV_SUPPORT
  892. env_init();
  893. env_load();
  894. if (env_get_yesno("boot_os") != 1)
  895. return 1;
  896. #endif
  897. return 0;
  898. }
  899. #endif
  900. #ifdef CONFIG_DRIVER_TI_CPSW
  901. extern u32 *const omap_si_rev;
  902. static void cpsw_control(int enabled)
  903. {
  904. /* VTP can be added here */
  905. return;
  906. }
  907. static struct cpsw_slave_data cpsw_slaves[] = {
  908. {
  909. .slave_reg_ofs = 0x208,
  910. .sliver_reg_ofs = 0xd80,
  911. .phy_addr = 2,
  912. },
  913. {
  914. .slave_reg_ofs = 0x308,
  915. .sliver_reg_ofs = 0xdc0,
  916. .phy_addr = 3,
  917. },
  918. };
  919. static struct cpsw_platform_data cpsw_data = {
  920. .mdio_base = CPSW_MDIO_BASE,
  921. .cpsw_base = CPSW_BASE,
  922. .mdio_div = 0xff,
  923. .channels = 8,
  924. .cpdma_reg_ofs = 0x800,
  925. .slaves = 2,
  926. .slave_data = cpsw_slaves,
  927. .ale_reg_ofs = 0xd00,
  928. .ale_entries = 1024,
  929. .host_port_reg_ofs = 0x108,
  930. .hw_stats_reg_ofs = 0x900,
  931. .bd_ram_ofs = 0x2000,
  932. .mac_control = (1 << 5),
  933. .control = cpsw_control,
  934. .host_port_num = 0,
  935. .version = CPSW_CTRL_VERSION_2,
  936. };
  937. int board_eth_init(bd_t *bis)
  938. {
  939. int ret;
  940. uint8_t mac_addr[6];
  941. uint32_t mac_hi, mac_lo;
  942. uint32_t ctrl_val;
  943. /* try reading mac address from efuse */
  944. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  945. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  946. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  947. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  948. mac_addr[2] = mac_hi & 0xFF;
  949. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  950. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  951. mac_addr[5] = mac_lo & 0xFF;
  952. if (!env_get("ethaddr")) {
  953. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  954. if (is_valid_ethaddr(mac_addr))
  955. eth_env_set_enetaddr("ethaddr", mac_addr);
  956. }
  957. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  958. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  959. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  960. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  961. mac_addr[2] = mac_hi & 0xFF;
  962. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  963. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  964. mac_addr[5] = mac_lo & 0xFF;
  965. if (!env_get("eth1addr")) {
  966. if (is_valid_ethaddr(mac_addr))
  967. eth_env_set_enetaddr("eth1addr", mac_addr);
  968. }
  969. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  970. ctrl_val |= 0x22;
  971. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  972. if (*omap_si_rev == DRA722_ES1_0)
  973. cpsw_data.active_slave = 1;
  974. if (board_is_dra72x_revc_or_later()) {
  975. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  976. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  977. }
  978. ret = cpsw_register(&cpsw_data);
  979. if (ret < 0)
  980. printf("Error %d registering CPSW switch\n", ret);
  981. return ret;
  982. }
  983. #endif
  984. #ifdef CONFIG_BOARD_EARLY_INIT_F
  985. /* VTT regulator enable */
  986. static inline void vtt_regulator_enable(void)
  987. {
  988. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  989. return;
  990. /* Do not enable VTT for DRA722 or DRA76x */
  991. if (is_dra72x() || is_dra76x())
  992. return;
  993. /*
  994. * EVM Rev G and later use gpio7_11 for DDR3 termination.
  995. * This is safe enough to do on older revs.
  996. */
  997. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  998. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  999. }
  1000. int board_early_init_f(void)
  1001. {
  1002. vtt_regulator_enable();
  1003. return 0;
  1004. }
  1005. #endif
  1006. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  1007. int ft_board_setup(void *blob, bd_t *bd)
  1008. {
  1009. ft_cpu_setup(blob, bd);
  1010. return 0;
  1011. }
  1012. #endif
  1013. #ifdef CONFIG_SPL_LOAD_FIT
  1014. int board_fit_config_name_match(const char *name)
  1015. {
  1016. if (is_dra72x()) {
  1017. if (board_is_dra71x_evm()) {
  1018. if (!strcmp(name, "dra71-evm"))
  1019. return 0;
  1020. }else if(board_is_dra72x_revc_or_later()) {
  1021. if (!strcmp(name, "dra72-evm-revc"))
  1022. return 0;
  1023. } else if (!strcmp(name, "dra72-evm")) {
  1024. return 0;
  1025. }
  1026. } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
  1027. return 0;
  1028. } else if (!is_dra72x() && !is_dra76x_acd() &&
  1029. !strcmp(name, "dra7-evm")) {
  1030. return 0;
  1031. }
  1032. return -1;
  1033. }
  1034. #endif
  1035. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  1036. int fastboot_set_reboot_flag(void)
  1037. {
  1038. printf("Setting reboot to fastboot flag ...\n");
  1039. env_set("dofastboot", "1");
  1040. env_save();
  1041. return 0;
  1042. }
  1043. #endif
  1044. #ifdef CONFIG_TI_SECURE_DEVICE
  1045. void board_fit_image_post_process(void **p_image, size_t *p_size)
  1046. {
  1047. secure_boot_verify_image(p_image, p_size);
  1048. }
  1049. void board_tee_image_process(ulong tee_image, size_t tee_size)
  1050. {
  1051. secure_tee_install((u32)tee_image);
  1052. }
  1053. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  1054. #endif