board.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  4. *
  5. * Author: Felipe Balbi <balbi@ti.com>
  6. *
  7. * Based on board/ti/dra7xx/evm.c
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <fdt_support.h>
  12. #include <init.h>
  13. #include <palmas.h>
  14. #include <sata.h>
  15. #include <serial.h>
  16. #include <usb.h>
  17. #include <asm/omap_common.h>
  18. #include <asm/omap_sec_common.h>
  19. #include <asm/emif.h>
  20. #include <asm/gpio.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/dra7xx_iodelay.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/arch/sata.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/omap.h>
  29. #include <usb.h>
  30. #include <linux/usb/gadget.h>
  31. #include <dwc3-uboot.h>
  32. #include <dwc3-omap-uboot.h>
  33. #include <ti-usb-phy-uboot.h>
  34. #include <mmc.h>
  35. #include <dm/uclass.h>
  36. #include "../common/board_detect.h"
  37. #include "mux_data.h"
  38. #define board_is_x15() board_ti_is("BBRDX15_")
  39. #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
  40. !strncmp("B.10", board_ti_get_rev(), 3))
  41. #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
  42. !strncmp("C.00", board_ti_get_rev(), 3))
  43. #define board_is_am572x_evm() board_ti_is("AM572PM_")
  44. #define board_is_am572x_evm_reva3() \
  45. (board_ti_is("AM572PM_") && \
  46. !strncmp("A.30", board_ti_get_rev(), 3))
  47. #define board_is_am574x_idk() board_ti_is("AM574IDK")
  48. #define board_is_am572x_idk() board_ti_is("AM572IDK")
  49. #define board_is_am571x_idk() board_ti_is("AM571IDK")
  50. #ifdef CONFIG_DRIVER_TI_CPSW
  51. #include <cpsw.h>
  52. #endif
  53. DECLARE_GLOBAL_DATA_PTR;
  54. #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
  55. /* GPIO 7_11 */
  56. #define GPIO_DDR_VTT_EN 203
  57. /* Touch screen controller to identify the LCD */
  58. #define OSD_TS_FT_BUS_ADDRESS 0
  59. #define OSD_TS_FT_CHIP_ADDRESS 0x38
  60. #define OSD_TS_FT_REG_ID 0xA3
  61. /*
  62. * Touchscreen IDs for various OSD panels
  63. * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  64. */
  65. /* Used on newer osd101t2587 Panels */
  66. #define OSD_TS_FT_ID_5x46 0x54
  67. /* Used on older osd101t2045 Panels */
  68. #define OSD_TS_FT_ID_5606 0x08
  69. #define SYSINFO_BOARD_NAME_MAX_LEN 45
  70. #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
  71. #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
  72. const struct omap_sysinfo sysinfo = {
  73. "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  74. };
  75. static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  76. .dmm_lisa_map_3 = 0x80740300,
  77. .is_ma_present = 0x1
  78. };
  79. static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  80. .dmm_lisa_map_3 = 0x80640100,
  81. .is_ma_present = 0x1
  82. };
  83. static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  84. .dmm_lisa_map_2 = 0xc0600200,
  85. .dmm_lisa_map_3 = 0x80600100,
  86. .is_ma_present = 0x1
  87. };
  88. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  89. {
  90. if (board_is_am571x_idk())
  91. *dmm_lisa_regs = &am571x_idk_lisa_regs;
  92. else if (board_is_am574x_idk())
  93. *dmm_lisa_regs = &am574x_idk_lisa_regs;
  94. else
  95. *dmm_lisa_regs = &beagle_x15_lisa_regs;
  96. }
  97. static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  98. .sdram_config_init = 0x61851b32,
  99. .sdram_config = 0x61851b32,
  100. .sdram_config2 = 0x08000000,
  101. .ref_ctrl = 0x000040F1,
  102. .ref_ctrl_final = 0x00001035,
  103. .sdram_tim1 = 0xcccf36ab,
  104. .sdram_tim2 = 0x308f7fda,
  105. .sdram_tim3 = 0x409f88a8,
  106. .read_idle_ctrl = 0x00050000,
  107. .zq_config = 0x5007190b,
  108. .temp_alert_config = 0x00000000,
  109. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  110. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  111. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  112. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  113. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  114. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  115. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  116. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  117. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  118. .emif_rd_wr_lvl_ctl = 0x00000000,
  119. .emif_rd_wr_exec_thresh = 0x00000305
  120. };
  121. /* Ext phy ctrl regs 1-35 */
  122. static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  123. 0x10040100,
  124. 0x00910091,
  125. 0x00950095,
  126. 0x009B009B,
  127. 0x009E009E,
  128. 0x00980098,
  129. 0x00340034,
  130. 0x00350035,
  131. 0x00340034,
  132. 0x00310031,
  133. 0x00340034,
  134. 0x007F007F,
  135. 0x007F007F,
  136. 0x007F007F,
  137. 0x007F007F,
  138. 0x007F007F,
  139. 0x00480048,
  140. 0x004A004A,
  141. 0x00520052,
  142. 0x00550055,
  143. 0x00500050,
  144. 0x00000000,
  145. 0x00600020,
  146. 0x40011080,
  147. 0x08102040,
  148. 0x0,
  149. 0x0,
  150. 0x0,
  151. 0x0,
  152. 0x0,
  153. 0x0,
  154. 0x0,
  155. 0x0,
  156. 0x0,
  157. 0x0
  158. };
  159. static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  160. .sdram_config_init = 0x61851b32,
  161. .sdram_config = 0x61851b32,
  162. .sdram_config2 = 0x08000000,
  163. .ref_ctrl = 0x000040F1,
  164. .ref_ctrl_final = 0x00001035,
  165. .sdram_tim1 = 0xcccf36b3,
  166. .sdram_tim2 = 0x308f7fda,
  167. .sdram_tim3 = 0x407f88a8,
  168. .read_idle_ctrl = 0x00050000,
  169. .zq_config = 0x5007190b,
  170. .temp_alert_config = 0x00000000,
  171. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  172. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  173. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  174. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  175. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  176. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  177. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  178. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  179. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  180. .emif_rd_wr_lvl_ctl = 0x00000000,
  181. .emif_rd_wr_exec_thresh = 0x00000305
  182. };
  183. static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  184. 0x10040100,
  185. 0x00910091,
  186. 0x00950095,
  187. 0x009B009B,
  188. 0x009E009E,
  189. 0x00980098,
  190. 0x00340034,
  191. 0x00350035,
  192. 0x00340034,
  193. 0x00310031,
  194. 0x00340034,
  195. 0x007F007F,
  196. 0x007F007F,
  197. 0x007F007F,
  198. 0x007F007F,
  199. 0x007F007F,
  200. 0x00480048,
  201. 0x004A004A,
  202. 0x00520052,
  203. 0x00550055,
  204. 0x00500050,
  205. 0x00000000,
  206. 0x00600020,
  207. 0x40011080,
  208. 0x08102040,
  209. 0x0,
  210. 0x0,
  211. 0x0,
  212. 0x0,
  213. 0x0,
  214. 0x0,
  215. 0x0,
  216. 0x0,
  217. 0x0,
  218. 0x0
  219. };
  220. static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
  221. .sdram_config_init = 0x61863332,
  222. .sdram_config = 0x61863332,
  223. .sdram_config2 = 0x08000000,
  224. .ref_ctrl = 0x0000514d,
  225. .ref_ctrl_final = 0x0000144a,
  226. .sdram_tim1 = 0xd333887c,
  227. .sdram_tim2 = 0x30b37fe3,
  228. .sdram_tim3 = 0x409f8ad8,
  229. .read_idle_ctrl = 0x00050000,
  230. .zq_config = 0x5007190b,
  231. .temp_alert_config = 0x00000000,
  232. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  233. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  234. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  235. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  236. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  237. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  238. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  239. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  240. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  241. .emif_rd_wr_lvl_ctl = 0x00000000,
  242. .emif_rd_wr_exec_thresh = 0x00000305
  243. };
  244. static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
  245. .sdram_config_init = 0x61863332,
  246. .sdram_config = 0x61863332,
  247. .sdram_config2 = 0x08000000,
  248. .ref_ctrl = 0x0000514d,
  249. .ref_ctrl_final = 0x0000144a,
  250. .sdram_tim1 = 0xd333887c,
  251. .sdram_tim2 = 0x30b37fe3,
  252. .sdram_tim3 = 0x409f8ad8,
  253. .read_idle_ctrl = 0x00050000,
  254. .zq_config = 0x5007190b,
  255. .temp_alert_config = 0x00000000,
  256. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  257. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  258. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  259. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  260. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  261. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  262. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  263. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  264. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  265. .emif_rd_wr_lvl_ctl = 0x00000000,
  266. .emif_rd_wr_exec_thresh = 0x00000305,
  267. .emif_ecc_ctrl_reg = 0xD0000001,
  268. .emif_ecc_address_range_1 = 0x3FFF0000,
  269. .emif_ecc_address_range_2 = 0x00000000
  270. };
  271. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  272. {
  273. switch (emif_nr) {
  274. case 1:
  275. if (board_is_am571x_idk())
  276. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  277. else if (board_is_am574x_idk())
  278. *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
  279. else
  280. *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  281. break;
  282. case 2:
  283. if (board_is_am574x_idk())
  284. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  285. else
  286. *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  287. break;
  288. }
  289. }
  290. void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  291. {
  292. switch (emif_nr) {
  293. case 1:
  294. *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  295. *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  296. break;
  297. case 2:
  298. *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  299. *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  300. break;
  301. }
  302. }
  303. struct vcores_data beagle_x15_volts = {
  304. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  305. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  306. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  307. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  308. .mpu.pmic = &tps659038,
  309. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  310. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  311. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  312. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  313. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  314. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  315. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  316. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  317. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  318. .eve.pmic = &tps659038,
  319. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  320. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  321. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  322. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  323. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  324. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  325. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  326. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  327. .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  328. .gpu.pmic = &tps659038,
  329. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  330. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  331. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  332. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  333. .core.addr = TPS659038_REG_ADDR_SMPS6,
  334. .core.pmic = &tps659038,
  335. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  336. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  337. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  338. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  339. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  340. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  341. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  342. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  343. .iva.pmic = &tps659038,
  344. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  345. };
  346. struct vcores_data am572x_idk_volts = {
  347. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  348. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  349. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  350. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  351. .mpu.pmic = &tps659038,
  352. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  353. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  354. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  355. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  356. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  357. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  358. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  359. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  360. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  361. .eve.pmic = &tps659038,
  362. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  363. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  364. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  365. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  366. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  367. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  368. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  369. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  370. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  371. .gpu.pmic = &tps659038,
  372. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  373. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  374. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  375. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  376. .core.addr = TPS659038_REG_ADDR_SMPS7,
  377. .core.pmic = &tps659038,
  378. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  379. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  380. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  381. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  382. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  383. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  384. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  385. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  386. .iva.pmic = &tps659038,
  387. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  388. };
  389. struct vcores_data am571x_idk_volts = {
  390. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  391. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  392. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  393. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  394. .mpu.pmic = &tps659038,
  395. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  396. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  397. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  398. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  399. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  400. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  401. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  402. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  403. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  404. .eve.pmic = &tps659038,
  405. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  406. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  407. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  408. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  409. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  410. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  411. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  412. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  413. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  414. .gpu.pmic = &tps659038,
  415. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  416. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  417. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  418. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  419. .core.addr = TPS659038_REG_ADDR_SMPS7,
  420. .core.pmic = &tps659038,
  421. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  422. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  423. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  424. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  425. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  426. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  427. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  428. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  429. .iva.pmic = &tps659038,
  430. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  431. };
  432. int get_voltrail_opp(int rail_offset)
  433. {
  434. int opp;
  435. switch (rail_offset) {
  436. case VOLT_MPU:
  437. opp = DRA7_MPU_OPP;
  438. break;
  439. case VOLT_CORE:
  440. opp = DRA7_CORE_OPP;
  441. break;
  442. case VOLT_GPU:
  443. opp = DRA7_GPU_OPP;
  444. break;
  445. case VOLT_EVE:
  446. opp = DRA7_DSPEVE_OPP;
  447. break;
  448. case VOLT_IVA:
  449. opp = DRA7_IVA_OPP;
  450. break;
  451. default:
  452. opp = OPP_NOM;
  453. }
  454. return opp;
  455. }
  456. #ifdef CONFIG_SPL_BUILD
  457. /* No env to setup for SPL */
  458. static inline void setup_board_eeprom_env(void) { }
  459. /* Override function to read eeprom information */
  460. void do_board_detect(void)
  461. {
  462. int rc;
  463. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  464. CONFIG_EEPROM_CHIP_ADDRESS);
  465. if (rc)
  466. printf("ti_i2c_eeprom_init failed %d\n", rc);
  467. }
  468. #else /* CONFIG_SPL_BUILD */
  469. /* Override function to read eeprom information: actual i2c read done by SPL*/
  470. void do_board_detect(void)
  471. {
  472. char *bname = NULL;
  473. int rc;
  474. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  475. CONFIG_EEPROM_CHIP_ADDRESS);
  476. if (rc)
  477. printf("ti_i2c_eeprom_init failed %d\n", rc);
  478. if (board_is_x15())
  479. bname = "BeagleBoard X15";
  480. else if (board_is_am572x_evm())
  481. bname = "AM572x EVM";
  482. else if (board_is_am574x_idk())
  483. bname = "AM574x IDK";
  484. else if (board_is_am572x_idk())
  485. bname = "AM572x IDK";
  486. else if (board_is_am571x_idk())
  487. bname = "AM571x IDK";
  488. if (bname)
  489. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  490. "Board: %s REV %s\n", bname, board_ti_get_rev());
  491. }
  492. static void setup_board_eeprom_env(void)
  493. {
  494. char *name = "beagle_x15";
  495. int rc;
  496. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  497. CONFIG_EEPROM_CHIP_ADDRESS);
  498. if (rc)
  499. goto invalid_eeprom;
  500. if (board_is_x15()) {
  501. if (board_is_x15_revb1())
  502. name = "beagle_x15_revb1";
  503. else if (board_is_x15_revc())
  504. name = "beagle_x15_revc";
  505. else
  506. name = "beagle_x15";
  507. } else if (board_is_am572x_evm()) {
  508. if (board_is_am572x_evm_reva3())
  509. name = "am57xx_evm_reva3";
  510. else
  511. name = "am57xx_evm";
  512. } else if (board_is_am574x_idk()) {
  513. name = "am574x_idk";
  514. } else if (board_is_am572x_idk()) {
  515. name = "am572x_idk";
  516. } else if (board_is_am571x_idk()) {
  517. name = "am571x_idk";
  518. } else {
  519. printf("Unidentified board claims %s in eeprom header\n",
  520. board_ti_get_name());
  521. }
  522. invalid_eeprom:
  523. set_board_info_env(name);
  524. }
  525. #endif /* CONFIG_SPL_BUILD */
  526. void vcores_init(void)
  527. {
  528. if (board_is_am572x_idk() || board_is_am574x_idk())
  529. *omap_vcores = &am572x_idk_volts;
  530. else if (board_is_am571x_idk())
  531. *omap_vcores = &am571x_idk_volts;
  532. else
  533. *omap_vcores = &beagle_x15_volts;
  534. }
  535. void hw_data_init(void)
  536. {
  537. *prcm = &dra7xx_prcm;
  538. if (is_dra72x())
  539. *dplls_data = &dra72x_dplls;
  540. else if (is_dra76x())
  541. *dplls_data = &dra76x_dplls;
  542. else
  543. *dplls_data = &dra7xx_dplls;
  544. *ctrl = &dra7xx_ctrl;
  545. }
  546. bool am571x_idk_needs_lcd(void)
  547. {
  548. bool needs_lcd;
  549. gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
  550. if (gpio_get_value(GPIO_ETH_LCD))
  551. needs_lcd = false;
  552. else
  553. needs_lcd = true;
  554. gpio_free(GPIO_ETH_LCD);
  555. return needs_lcd;
  556. }
  557. int board_init(void)
  558. {
  559. gpmc_init();
  560. gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  561. return 0;
  562. }
  563. void am57x_idk_lcd_detect(void)
  564. {
  565. int r = -ENODEV;
  566. char *idk_lcd = "no";
  567. struct udevice *dev;
  568. /* Only valid for IDKs */
  569. if (board_is_x15() || board_is_am572x_evm())
  570. return;
  571. /* Only AM571x IDK has gpio control detect.. so check that */
  572. if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
  573. goto out;
  574. r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
  575. OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
  576. if (r) {
  577. printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
  578. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  579. r);
  580. /* AM572x IDK has no explicit settings for optional LCD kit */
  581. if (board_is_am571x_idk())
  582. printf("%s: Touch screen detect failed: %d!\n",
  583. __func__, r);
  584. goto out;
  585. }
  586. /* Read FT ID */
  587. r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
  588. if (r < 0) {
  589. printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
  590. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  591. OSD_TS_FT_REG_ID, r);
  592. goto out;
  593. }
  594. switch (r) {
  595. case OSD_TS_FT_ID_5606:
  596. idk_lcd = "osd101t2045";
  597. break;
  598. case OSD_TS_FT_ID_5x46:
  599. idk_lcd = "osd101t2587";
  600. break;
  601. default:
  602. printf("%s: Unidentifed Touch screen ID 0x%02x\n",
  603. __func__, r);
  604. /* we will let default be "no lcd" */
  605. }
  606. out:
  607. env_set("idk_lcd", idk_lcd);
  608. return;
  609. }
  610. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  611. static int device_okay(const char *path)
  612. {
  613. int node;
  614. node = fdt_path_offset(gd->fdt_blob, path);
  615. if (node < 0)
  616. return 0;
  617. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  618. }
  619. #endif
  620. int board_late_init(void)
  621. {
  622. setup_board_eeprom_env();
  623. u8 val;
  624. struct udevice *dev;
  625. /*
  626. * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  627. * This is the POWERHOLD-in-Low behavior.
  628. */
  629. palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  630. /*
  631. * Default FIT boot on HS devices. Non FIT images are not allowed
  632. * on HS devices.
  633. */
  634. if (get_device_type() == HS_DEVICE)
  635. env_set("boot_fit", "1");
  636. /*
  637. * Set the GPIO7 Pad to POWERHOLD. This has higher priority
  638. * over DEV_CTRL.DEV_ON bit. This can be reset in case of
  639. * PMIC Power off. So to be on the safer side set it back
  640. * to POWERHOLD mode irrespective of the current state.
  641. */
  642. palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  643. &val);
  644. val = val | TPS65903X_PAD2_POWERHOLD_MASK;
  645. palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  646. val);
  647. omap_die_id_serial();
  648. omap_set_fastboot_vars();
  649. am57x_idk_lcd_detect();
  650. /* Just probe the potentially supported cdce913 device */
  651. uclass_get_device(UCLASS_CLK, 0, &dev);
  652. #if !defined(CONFIG_SPL_BUILD)
  653. board_ti_set_ethaddr(2);
  654. #endif
  655. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  656. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  657. enable_usb_clocks(0);
  658. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  659. enable_usb_clocks(1);
  660. #endif
  661. return 0;
  662. }
  663. void set_muxconf_regs(void)
  664. {
  665. do_set_mux32((*ctrl)->control_padconf_core_base,
  666. early_padconf, ARRAY_SIZE(early_padconf));
  667. }
  668. #ifdef CONFIG_IODELAY_RECALIBRATION
  669. void recalibrate_iodelay(void)
  670. {
  671. const struct pad_conf_entry *pconf;
  672. const struct iodelay_cfg_entry *iod, *delta_iod;
  673. int pconf_sz, iod_sz, delta_iod_sz = 0;
  674. int ret;
  675. if (board_is_am572x_idk()) {
  676. pconf = core_padconf_array_essential_am572x_idk;
  677. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
  678. iod = iodelay_cfg_array_am572x_idk;
  679. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
  680. } else if (board_is_am574x_idk()) {
  681. pconf = core_padconf_array_essential_am574x_idk;
  682. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
  683. iod = iodelay_cfg_array_am574x_idk;
  684. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
  685. } else if (board_is_am571x_idk()) {
  686. pconf = core_padconf_array_essential_am571x_idk;
  687. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
  688. iod = iodelay_cfg_array_am571x_idk;
  689. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
  690. } else {
  691. /* Common for X15/GPEVM */
  692. pconf = core_padconf_array_essential_x15;
  693. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
  694. /* There never was an SR1.0 X15.. So.. */
  695. if (omap_revision() == DRA752_ES1_1) {
  696. iod = iodelay_cfg_array_x15_sr1_1;
  697. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
  698. } else {
  699. /* Since full production should switch to SR2.0 */
  700. iod = iodelay_cfg_array_x15_sr2_0;
  701. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
  702. }
  703. }
  704. /* Setup I/O isolation */
  705. ret = __recalibrate_iodelay_start();
  706. if (ret)
  707. goto err;
  708. /* Do the muxing here */
  709. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  710. /* Now do the weird minor deltas that should be safe */
  711. if (board_is_x15() || board_is_am572x_evm()) {
  712. if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
  713. board_is_x15_revc()) {
  714. pconf = core_padconf_array_delta_x15_sr2_0;
  715. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
  716. } else {
  717. pconf = core_padconf_array_delta_x15_sr1_1;
  718. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
  719. }
  720. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  721. }
  722. if (board_is_am571x_idk()) {
  723. if (am571x_idk_needs_lcd()) {
  724. pconf = core_padconf_array_vout_am571x_idk;
  725. pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
  726. delta_iod = iodelay_cfg_array_am571x_idk_4port;
  727. delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
  728. } else {
  729. pconf = core_padconf_array_icss1eth_am571x_idk;
  730. pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
  731. }
  732. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  733. }
  734. /* Setup IOdelay configuration */
  735. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
  736. if (delta_iod_sz)
  737. ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
  738. delta_iod_sz);
  739. err:
  740. /* Closeup.. remove isolation */
  741. __recalibrate_iodelay_end(ret);
  742. }
  743. #endif
  744. #if defined(CONFIG_MMC)
  745. int board_mmc_init(bd_t *bis)
  746. {
  747. omap_mmc_init(0, 0, 0, -1, -1);
  748. omap_mmc_init(1, 0, 0, -1, -1);
  749. return 0;
  750. }
  751. static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
  752. .hw_rev = "rev11",
  753. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  754. MMC_CAP(UHS_SDR104),
  755. .max_freq = 96000000,
  756. };
  757. static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
  758. .hw_rev = "rev11",
  759. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  760. MMC_CAP(UHS_SDR104) |
  761. MMC_CAP(UHS_SDR50),
  762. .max_freq = 48000000,
  763. };
  764. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  765. {
  766. switch (omap_revision()) {
  767. case DRA752_ES1_0:
  768. case DRA752_ES1_1:
  769. if (addr == OMAP_HSMMC1_BASE)
  770. return &am57x_es1_1_mmc1_fixups;
  771. else
  772. return &am57x_es1_1_mmc23_fixups;
  773. default:
  774. return NULL;
  775. }
  776. }
  777. #endif
  778. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  779. int spl_start_uboot(void)
  780. {
  781. /* break into full u-boot on 'c' */
  782. if (serial_tstc() && serial_getc() == 'c')
  783. return 1;
  784. #ifdef CONFIG_SPL_ENV_SUPPORT
  785. env_init();
  786. env_load();
  787. if (env_get_yesno("boot_os") != 1)
  788. return 1;
  789. #endif
  790. return 0;
  791. }
  792. #endif
  793. #ifdef CONFIG_DRIVER_TI_CPSW
  794. /* Delay value to add to calibrated value */
  795. #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  796. #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  797. #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  798. #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  799. #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  800. #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  801. #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  802. #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  803. #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  804. #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  805. static void cpsw_control(int enabled)
  806. {
  807. /* VTP can be added here */
  808. }
  809. static struct cpsw_slave_data cpsw_slaves[] = {
  810. {
  811. .slave_reg_ofs = 0x208,
  812. .sliver_reg_ofs = 0xd80,
  813. .phy_addr = 1,
  814. },
  815. {
  816. .slave_reg_ofs = 0x308,
  817. .sliver_reg_ofs = 0xdc0,
  818. .phy_addr = 2,
  819. },
  820. };
  821. static struct cpsw_platform_data cpsw_data = {
  822. .mdio_base = CPSW_MDIO_BASE,
  823. .cpsw_base = CPSW_BASE,
  824. .mdio_div = 0xff,
  825. .channels = 8,
  826. .cpdma_reg_ofs = 0x800,
  827. .slaves = 1,
  828. .slave_data = cpsw_slaves,
  829. .ale_reg_ofs = 0xd00,
  830. .ale_entries = 1024,
  831. .host_port_reg_ofs = 0x108,
  832. .hw_stats_reg_ofs = 0x900,
  833. .bd_ram_ofs = 0x2000,
  834. .mac_control = (1 << 5),
  835. .control = cpsw_control,
  836. .host_port_num = 0,
  837. .version = CPSW_CTRL_VERSION_2,
  838. };
  839. static u64 mac_to_u64(u8 mac[6])
  840. {
  841. int i;
  842. u64 addr = 0;
  843. for (i = 0; i < 6; i++) {
  844. addr <<= 8;
  845. addr |= mac[i];
  846. }
  847. return addr;
  848. }
  849. static void u64_to_mac(u64 addr, u8 mac[6])
  850. {
  851. mac[5] = addr;
  852. mac[4] = addr >> 8;
  853. mac[3] = addr >> 16;
  854. mac[2] = addr >> 24;
  855. mac[1] = addr >> 32;
  856. mac[0] = addr >> 40;
  857. }
  858. int board_eth_init(bd_t *bis)
  859. {
  860. int ret;
  861. uint8_t mac_addr[6];
  862. uint32_t mac_hi, mac_lo;
  863. uint32_t ctrl_val;
  864. int i;
  865. u64 mac1, mac2;
  866. u8 mac_addr1[6], mac_addr2[6];
  867. int num_macs;
  868. /* try reading mac address from efuse */
  869. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  870. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  871. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  872. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  873. mac_addr[2] = mac_hi & 0xFF;
  874. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  875. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  876. mac_addr[5] = mac_lo & 0xFF;
  877. if (!env_get("ethaddr")) {
  878. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  879. if (is_valid_ethaddr(mac_addr))
  880. eth_env_set_enetaddr("ethaddr", mac_addr);
  881. }
  882. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  883. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  884. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  885. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  886. mac_addr[2] = mac_hi & 0xFF;
  887. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  888. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  889. mac_addr[5] = mac_lo & 0xFF;
  890. if (!env_get("eth1addr")) {
  891. if (is_valid_ethaddr(mac_addr))
  892. eth_env_set_enetaddr("eth1addr", mac_addr);
  893. }
  894. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  895. ctrl_val |= 0x22;
  896. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  897. /* The phy address for the AM57xx IDK are different than x15 */
  898. if (board_is_am572x_idk() || board_is_am571x_idk() ||
  899. board_is_am574x_idk()) {
  900. cpsw_data.slave_data[0].phy_addr = 0;
  901. cpsw_data.slave_data[1].phy_addr = 1;
  902. }
  903. ret = cpsw_register(&cpsw_data);
  904. if (ret < 0)
  905. printf("Error %d registering CPSW switch\n", ret);
  906. /*
  907. * Export any Ethernet MAC addresses from EEPROM.
  908. * On AM57xx the 2 MAC addresses define the address range
  909. */
  910. board_ti_get_eth_mac_addr(0, mac_addr1);
  911. board_ti_get_eth_mac_addr(1, mac_addr2);
  912. if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
  913. mac1 = mac_to_u64(mac_addr1);
  914. mac2 = mac_to_u64(mac_addr2);
  915. /* must contain an address range */
  916. num_macs = mac2 - mac1 + 1;
  917. /* <= 50 to protect against user programming error */
  918. if (num_macs > 0 && num_macs <= 50) {
  919. for (i = 0; i < num_macs; i++) {
  920. u64_to_mac(mac1 + i, mac_addr);
  921. if (is_valid_ethaddr(mac_addr)) {
  922. eth_env_set_enetaddr_by_index("eth",
  923. i + 2,
  924. mac_addr);
  925. }
  926. }
  927. }
  928. }
  929. return ret;
  930. }
  931. #endif
  932. #ifdef CONFIG_BOARD_EARLY_INIT_F
  933. /* VTT regulator enable */
  934. static inline void vtt_regulator_enable(void)
  935. {
  936. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  937. return;
  938. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  939. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  940. }
  941. int board_early_init_f(void)
  942. {
  943. vtt_regulator_enable();
  944. return 0;
  945. }
  946. #endif
  947. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  948. int ft_board_setup(void *blob, bd_t *bd)
  949. {
  950. ft_cpu_setup(blob, bd);
  951. return 0;
  952. }
  953. #endif
  954. #ifdef CONFIG_SPL_LOAD_FIT
  955. int board_fit_config_name_match(const char *name)
  956. {
  957. if (board_is_x15()) {
  958. if (board_is_x15_revb1()) {
  959. if (!strcmp(name, "am57xx-beagle-x15-revb1"))
  960. return 0;
  961. } else if (board_is_x15_revc()) {
  962. if (!strcmp(name, "am57xx-beagle-x15-revc"))
  963. return 0;
  964. } else if (!strcmp(name, "am57xx-beagle-x15")) {
  965. return 0;
  966. }
  967. } else if (board_is_am572x_evm() &&
  968. !strcmp(name, "am57xx-beagle-x15")) {
  969. return 0;
  970. } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
  971. return 0;
  972. } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
  973. return 0;
  974. } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
  975. return 0;
  976. }
  977. return -1;
  978. }
  979. #endif
  980. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  981. int fastboot_set_reboot_flag(void)
  982. {
  983. printf("Setting reboot to fastboot flag ...\n");
  984. env_set("dofastboot", "1");
  985. env_save();
  986. return 0;
  987. }
  988. #endif
  989. #ifdef CONFIG_TI_SECURE_DEVICE
  990. void board_fit_image_post_process(void **p_image, size_t *p_size)
  991. {
  992. secure_boot_verify_image(p_image, p_size);
  993. }
  994. void board_tee_image_process(ulong tee_image, size_t tee_size)
  995. {
  996. secure_tee_install((u32)tee_image);
  997. }
  998. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  999. #endif