board.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM43XX based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <eeprom.h>
  11. #include <env.h>
  12. #include <fdt_support.h>
  13. #include <i2c.h>
  14. #include <init.h>
  15. #include <linux/errno.h>
  16. #include <spl.h>
  17. #include <usb.h>
  18. #include <asm/omap_sec_common.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/arch/mux.h>
  22. #include <asm/arch/ddr_defs.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/emif.h>
  25. #include <asm/omap_common.h>
  26. #include "../common/board_detect.h"
  27. #include "board.h"
  28. #include <power/pmic.h>
  29. #include <power/tps65218.h>
  30. #include <power/tps62362.h>
  31. #include <miiphy.h>
  32. #include <cpsw.h>
  33. #include <linux/usb/gadget.h>
  34. #include <dwc3-uboot.h>
  35. #include <dwc3-omap-uboot.h>
  36. #include <ti-usb-phy-uboot.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39. /*
  40. * Read header information from EEPROM into global structure.
  41. */
  42. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  43. void do_board_detect(void)
  44. {
  45. /* Ensure I2C is initialized for EEPROM access*/
  46. gpi2c_init();
  47. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  48. CONFIG_EEPROM_CHIP_ADDRESS))
  49. printf("ti_i2c_eeprom_init failed\n");
  50. }
  51. #endif
  52. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  53. const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  54. { /* 19.2 MHz */
  55. {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
  56. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  57. {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
  58. {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
  59. {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  60. {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
  61. },
  62. { /* 24 MHz */
  63. {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
  64. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  65. {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
  66. {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
  67. {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
  68. {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
  69. },
  70. { /* 25 MHz */
  71. {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
  72. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  73. {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
  74. {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
  75. {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
  76. {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
  77. },
  78. { /* 26 MHz */
  79. {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
  80. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  81. {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
  82. {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
  83. {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
  84. {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
  85. },
  86. };
  87. const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  88. {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
  89. {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
  90. {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
  91. {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
  92. };
  93. const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  94. {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  95. {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
  96. {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
  97. {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
  98. };
  99. const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
  100. {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
  101. {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
  102. {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
  103. {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
  104. };
  105. const struct dpll_params gp_evm_dpll_ddr = {
  106. 50, 2, 1, -1, 2, -1, -1};
  107. static const struct dpll_params idk_dpll_ddr = {
  108. 400, 23, 1, -1, 2, -1, -1
  109. };
  110. static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
  111. 0x00500050,
  112. 0x00350035,
  113. 0x00350035,
  114. 0x00350035,
  115. 0x00350035,
  116. 0x00350035,
  117. 0x00000000,
  118. 0x00000000,
  119. 0x00000000,
  120. 0x00000000,
  121. 0x00000000,
  122. 0x00000000,
  123. 0x00000000,
  124. 0x00000000,
  125. 0x00000000,
  126. 0x00000000,
  127. 0x00000000,
  128. 0x00000000,
  129. 0x40001000,
  130. 0x08102040
  131. };
  132. const struct ctrl_ioregs ioregs_lpddr2 = {
  133. .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
  134. .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
  135. .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
  136. .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  137. .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  138. .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  139. .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  140. .emif_sdram_config_ext = 0x1,
  141. };
  142. const struct emif_regs emif_regs_lpddr2 = {
  143. .sdram_config = 0x808012BA,
  144. .ref_ctrl = 0x0000040D,
  145. .sdram_tim1 = 0xEA86B411,
  146. .sdram_tim2 = 0x103A094A,
  147. .sdram_tim3 = 0x0F6BA37F,
  148. .read_idle_ctrl = 0x00050000,
  149. .zq_config = 0x50074BE4,
  150. .temp_alert_config = 0x0,
  151. .emif_rd_wr_lvl_rmp_win = 0x0,
  152. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  153. .emif_rd_wr_lvl_ctl = 0x0,
  154. .emif_ddr_phy_ctlr_1 = 0x0E284006,
  155. .emif_rd_wr_exec_thresh = 0x80000405,
  156. .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
  157. .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
  158. .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
  159. .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
  160. .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
  161. .emif_prio_class_serv_map = 0x80000001,
  162. .emif_connect_id_serv_1_map = 0x80000094,
  163. .emif_connect_id_serv_2_map = 0x00000000,
  164. .emif_cos_config = 0x000FFFFF
  165. };
  166. const struct ctrl_ioregs ioregs_ddr3 = {
  167. .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
  168. .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  169. .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  170. .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
  171. .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
  172. .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  173. .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  174. .emif_sdram_config_ext = 0xc163,
  175. };
  176. const struct emif_regs ddr3_emif_regs_400Mhz = {
  177. .sdram_config = 0x638413B2,
  178. .ref_ctrl = 0x00000C30,
  179. .sdram_tim1 = 0xEAAAD4DB,
  180. .sdram_tim2 = 0x266B7FDA,
  181. .sdram_tim3 = 0x107F8678,
  182. .read_idle_ctrl = 0x00050000,
  183. .zq_config = 0x50074BE4,
  184. .temp_alert_config = 0x0,
  185. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  186. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  187. .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
  188. .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
  189. .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
  190. .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
  191. .emif_rd_wr_lvl_rmp_win = 0x0,
  192. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  193. .emif_rd_wr_lvl_ctl = 0x0,
  194. .emif_rd_wr_exec_thresh = 0x80000405,
  195. .emif_prio_class_serv_map = 0x80000001,
  196. .emif_connect_id_serv_1_map = 0x80000094,
  197. .emif_connect_id_serv_2_map = 0x00000000,
  198. .emif_cos_config = 0x000FFFFF
  199. };
  200. /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
  201. const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
  202. .sdram_config = 0x638413B2,
  203. .ref_ctrl = 0x00000C30,
  204. .sdram_tim1 = 0xEAAAD4DB,
  205. .sdram_tim2 = 0x266B7FDA,
  206. .sdram_tim3 = 0x107F8678,
  207. .read_idle_ctrl = 0x00050000,
  208. .zq_config = 0x50074BE4,
  209. .temp_alert_config = 0x0,
  210. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  211. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  212. .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
  213. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  214. .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
  215. .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
  216. .emif_rd_wr_exec_thresh = 0x80000405,
  217. .emif_prio_class_serv_map = 0x80000001,
  218. .emif_connect_id_serv_1_map = 0x80000094,
  219. .emif_connect_id_serv_2_map = 0x00000000,
  220. .emif_cos_config = 0x000FFFFF
  221. };
  222. /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  223. const struct emif_regs ddr3_emif_regs_400Mhz_production = {
  224. .sdram_config = 0x638413B2,
  225. .ref_ctrl = 0x00000C30,
  226. .sdram_tim1 = 0xEAAAD4DB,
  227. .sdram_tim2 = 0x266B7FDA,
  228. .sdram_tim3 = 0x107F8678,
  229. .read_idle_ctrl = 0x00050000,
  230. .zq_config = 0x50074BE4,
  231. .temp_alert_config = 0x0,
  232. .emif_ddr_phy_ctlr_1 = 0x00048008,
  233. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  234. .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
  235. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  236. .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
  237. .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
  238. .emif_rd_wr_exec_thresh = 0x80000405,
  239. .emif_prio_class_serv_map = 0x80000001,
  240. .emif_connect_id_serv_1_map = 0x80000094,
  241. .emif_connect_id_serv_2_map = 0x00000000,
  242. .emif_cos_config = 0x000FFFFF
  243. };
  244. static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
  245. .sdram_config = 0x638413b2,
  246. .sdram_config2 = 0x00000000,
  247. .ref_ctrl = 0x00000c30,
  248. .sdram_tim1 = 0xeaaad4db,
  249. .sdram_tim2 = 0x266b7fda,
  250. .sdram_tim3 = 0x107f8678,
  251. .read_idle_ctrl = 0x00050000,
  252. .zq_config = 0x50074be4,
  253. .temp_alert_config = 0x0,
  254. .emif_ddr_phy_ctlr_1 = 0x0e084008,
  255. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  256. .emif_ddr_ext_phy_ctrl_2 = 0x89,
  257. .emif_ddr_ext_phy_ctrl_3 = 0x90,
  258. .emif_ddr_ext_phy_ctrl_4 = 0x8e,
  259. .emif_ddr_ext_phy_ctrl_5 = 0x8d,
  260. .emif_rd_wr_lvl_rmp_win = 0x0,
  261. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  262. .emif_rd_wr_lvl_ctl = 0x00000000,
  263. .emif_rd_wr_exec_thresh = 0x80000000,
  264. .emif_prio_class_serv_map = 0x80000001,
  265. .emif_connect_id_serv_1_map = 0x80000094,
  266. .emif_connect_id_serv_2_map = 0x00000000,
  267. .emif_cos_config = 0x000FFFFF
  268. };
  269. static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
  270. .sdram_config = 0x61a11b32,
  271. .sdram_config2 = 0x00000000,
  272. .ref_ctrl = 0x00000c30,
  273. .sdram_tim1 = 0xeaaad4db,
  274. .sdram_tim2 = 0x266b7fda,
  275. .sdram_tim3 = 0x107f8678,
  276. .read_idle_ctrl = 0x00050000,
  277. .zq_config = 0x50074be4,
  278. .temp_alert_config = 0x00000000,
  279. .emif_ddr_phy_ctlr_1 = 0x00008009,
  280. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  281. .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
  282. .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
  283. .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
  284. .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
  285. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  286. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  287. .emif_rd_wr_lvl_ctl = 0x00000000,
  288. .emif_rd_wr_exec_thresh = 0x00000405,
  289. .emif_prio_class_serv_map = 0x00000000,
  290. .emif_connect_id_serv_1_map = 0x00000000,
  291. .emif_connect_id_serv_2_map = 0x00000000,
  292. .emif_cos_config = 0x00ffffff
  293. };
  294. void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  295. {
  296. if (board_is_eposevm()) {
  297. *regs = ext_phy_ctrl_const_base_lpddr2;
  298. *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
  299. }
  300. return;
  301. }
  302. const struct dpll_params *get_dpll_ddr_params(void)
  303. {
  304. int ind = get_sys_clk_index();
  305. if (board_is_eposevm())
  306. return &epos_evm_dpll_ddr[ind];
  307. else if (board_is_evm() || board_is_sk())
  308. return &gp_evm_dpll_ddr;
  309. else if (board_is_idk())
  310. return &idk_dpll_ddr;
  311. printf(" Board '%s' not supported\n", board_ti_get_name());
  312. return NULL;
  313. }
  314. /*
  315. * get_opp_offset:
  316. * Returns the index for safest OPP of the device to boot.
  317. * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
  318. * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
  319. * This data is read from dev_attribute register which is e-fused.
  320. * A'1' in bit indicates OPP disabled and not available, a '0' indicates
  321. * OPP available. Lowest OPP starts with min_off. So returning the
  322. * bit with rightmost '0'.
  323. */
  324. static int get_opp_offset(int max_off, int min_off)
  325. {
  326. struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
  327. int opp, offset, i;
  328. /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
  329. opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
  330. for (i = max_off; i >= min_off; i--) {
  331. offset = opp & (1 << i);
  332. if (!offset)
  333. return i;
  334. }
  335. return min_off;
  336. }
  337. const struct dpll_params *get_dpll_mpu_params(void)
  338. {
  339. int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
  340. u32 ind = get_sys_clk_index();
  341. return &dpll_mpu[ind][opp];
  342. }
  343. const struct dpll_params *get_dpll_core_params(void)
  344. {
  345. int ind = get_sys_clk_index();
  346. return &dpll_core[ind];
  347. }
  348. const struct dpll_params *get_dpll_per_params(void)
  349. {
  350. int ind = get_sys_clk_index();
  351. return &dpll_per[ind];
  352. }
  353. void scale_vcores_generic(u32 m)
  354. {
  355. int mpu_vdd, ddr_volt;
  356. #ifndef CONFIG_DM_I2C
  357. if (i2c_probe(TPS65218_CHIP_PM))
  358. return;
  359. #else
  360. if (power_tps65218_init(0))
  361. return;
  362. #endif
  363. switch (m) {
  364. case 1000:
  365. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
  366. break;
  367. case 800:
  368. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
  369. break;
  370. case 720:
  371. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
  372. break;
  373. case 600:
  374. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
  375. break;
  376. case 300:
  377. mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
  378. break;
  379. default:
  380. puts("Unknown MPU clock, not scaling\n");
  381. return;
  382. }
  383. /* Set DCDC1 (CORE) voltage to 1.1V */
  384. if (tps65218_voltage_update(TPS65218_DCDC1,
  385. TPS65218_DCDC_VOLT_SEL_1100MV)) {
  386. printf("%s failure\n", __func__);
  387. return;
  388. }
  389. /* Set DCDC2 (MPU) voltage */
  390. if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
  391. printf("%s failure\n", __func__);
  392. return;
  393. }
  394. if (board_is_eposevm())
  395. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
  396. else
  397. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
  398. /* Set DCDC3 (DDR) voltage */
  399. if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
  400. printf("%s failure\n", __func__);
  401. return;
  402. }
  403. }
  404. void scale_vcores_idk(u32 m)
  405. {
  406. int mpu_vdd;
  407. #ifndef CONFIG_DM_I2C
  408. if (i2c_probe(TPS62362_I2C_ADDR))
  409. return;
  410. #else
  411. if (power_tps62362_init(0))
  412. return;
  413. #endif
  414. switch (m) {
  415. case 1000:
  416. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  417. break;
  418. case 800:
  419. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
  420. break;
  421. case 720:
  422. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
  423. break;
  424. case 600:
  425. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
  426. break;
  427. case 300:
  428. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  429. break;
  430. default:
  431. puts("Unknown MPU clock, not scaling\n");
  432. return;
  433. }
  434. /* Set VDD_MPU voltage */
  435. if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
  436. printf("%s failure\n", __func__);
  437. return;
  438. }
  439. }
  440. void gpi2c_init(void)
  441. {
  442. /* When needed to be invoked prior to BSS initialization */
  443. static bool first_time = true;
  444. if (first_time) {
  445. enable_i2c0_pin_mux();
  446. #ifndef CONFIG_DM_I2C
  447. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  448. CONFIG_SYS_OMAP24_I2C_SLAVE);
  449. #endif
  450. first_time = false;
  451. }
  452. }
  453. void scale_vcores(void)
  454. {
  455. const struct dpll_params *mpu_params;
  456. /* Ensure I2C is initialized for PMIC configuration */
  457. gpi2c_init();
  458. /* Get the frequency */
  459. mpu_params = get_dpll_mpu_params();
  460. if (board_is_idk())
  461. scale_vcores_idk(mpu_params->m);
  462. else
  463. scale_vcores_generic(mpu_params->m);
  464. }
  465. void set_uart_mux_conf(void)
  466. {
  467. enable_uart0_pin_mux();
  468. }
  469. void set_mux_conf_regs(void)
  470. {
  471. enable_board_pin_mux();
  472. }
  473. static void enable_vtt_regulator(void)
  474. {
  475. u32 temp;
  476. /* enable module */
  477. writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
  478. /* enable output for GPIO5_7 */
  479. writel(GPIO_SETDATAOUT(7),
  480. AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
  481. temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  482. temp = temp & ~(GPIO_OE_ENABLE(7));
  483. writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  484. }
  485. enum {
  486. RTC_BOARD_EPOS = 1,
  487. RTC_BOARD_EVM14,
  488. RTC_BOARD_EVM12,
  489. RTC_BOARD_GPEVM,
  490. RTC_BOARD_SK,
  491. };
  492. /*
  493. * In the rtc_only+DRR in self-refresh boot path we have the board type info
  494. * in the rtc scratch pad register hence we bypass the costly i2c reads to
  495. * eeprom and directly programthe board name string
  496. */
  497. void rtc_only_update_board_type(u32 btype)
  498. {
  499. const char *name = "";
  500. const char *rev = "1.0";
  501. switch (btype) {
  502. case RTC_BOARD_EPOS:
  503. name = "AM43EPOS";
  504. break;
  505. case RTC_BOARD_EVM14:
  506. name = "AM43__GP";
  507. rev = "1.4";
  508. break;
  509. case RTC_BOARD_EVM12:
  510. name = "AM43__GP";
  511. rev = "1.2";
  512. break;
  513. case RTC_BOARD_GPEVM:
  514. name = "AM43__GP";
  515. break;
  516. case RTC_BOARD_SK:
  517. name = "AM43__SK";
  518. break;
  519. }
  520. ti_i2c_eeprom_am_set(name, rev);
  521. }
  522. u32 rtc_only_get_board_type(void)
  523. {
  524. if (board_is_eposevm())
  525. return RTC_BOARD_EPOS;
  526. else if (board_is_evm_14_or_later())
  527. return RTC_BOARD_EVM14;
  528. else if (board_is_evm_12_or_later())
  529. return RTC_BOARD_EVM12;
  530. else if (board_is_gpevm())
  531. return RTC_BOARD_GPEVM;
  532. else if (board_is_sk())
  533. return RTC_BOARD_SK;
  534. return 0;
  535. }
  536. void sdram_init(void)
  537. {
  538. /*
  539. * EPOS EVM has 1GB LPDDR2 connected to EMIF.
  540. * GP EMV has 1GB DDR3 connected to EMIF
  541. * along with VTT regulator.
  542. */
  543. if (board_is_eposevm()) {
  544. config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
  545. } else if (board_is_evm_14_or_later()) {
  546. enable_vtt_regulator();
  547. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  548. &ddr3_emif_regs_400Mhz_production, 0);
  549. } else if (board_is_evm_12_or_later()) {
  550. enable_vtt_regulator();
  551. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  552. &ddr3_emif_regs_400Mhz_beta, 0);
  553. } else if (board_is_evm()) {
  554. enable_vtt_regulator();
  555. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  556. &ddr3_emif_regs_400Mhz, 0);
  557. } else if (board_is_sk()) {
  558. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  559. &ddr3_sk_emif_regs_400Mhz, 0);
  560. } else if (board_is_idk()) {
  561. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  562. &ddr3_idk_emif_regs_400Mhz, 0);
  563. }
  564. }
  565. #endif
  566. /* setup board specific PMIC */
  567. int power_init_board(void)
  568. {
  569. int rc;
  570. #ifndef CONFIG_DM_I2C
  571. struct pmic *p = NULL;
  572. #endif
  573. if (board_is_idk()) {
  574. rc = power_tps62362_init(0);
  575. if (rc)
  576. goto done;
  577. #ifndef CONFIG_DM_I2C
  578. p = pmic_get("TPS62362");
  579. if (!p || pmic_probe(p))
  580. goto done;
  581. #endif
  582. puts("PMIC: TPS62362\n");
  583. } else {
  584. rc = power_tps65218_init(0);
  585. if (rc)
  586. goto done;
  587. #ifndef CONFIG_DM_I2C
  588. p = pmic_get("TPS65218_PMIC");
  589. if (!p || pmic_probe(p))
  590. goto done;
  591. #endif
  592. puts("PMIC: TPS65218\n");
  593. }
  594. done:
  595. return 0;
  596. }
  597. int board_init(void)
  598. {
  599. struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
  600. u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
  601. modena_init0_bw_integer, modena_init0_watermark_0;
  602. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  603. gpmc_init();
  604. /*
  605. * Call this to initialize *ctrl again
  606. */
  607. hw_data_init();
  608. /* Clear all important bits for DSS errata that may need to be tweaked*/
  609. mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
  610. MREQPRIO_0_SAB_INIT0_MASK;
  611. mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
  612. modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
  613. BW_LIMITER_BW_FRAC_MASK;
  614. modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
  615. BW_LIMITER_BW_INT_MASK;
  616. modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
  617. BW_LIMITER_BW_WATERMARK_MASK;
  618. /* Setting MReq Priority of the DSS*/
  619. mreqprio_0 |= 0x77;
  620. /*
  621. * Set L3 Fast Configuration Register
  622. * Limiting bandwith for ARM core to 700 MBPS
  623. */
  624. modena_init0_bw_fractional |= 0x10;
  625. modena_init0_bw_integer |= 0x3;
  626. writel(mreqprio_0, &cdev->mreqprio_0);
  627. writel(mreqprio_1, &cdev->mreqprio_1);
  628. writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
  629. writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
  630. writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
  631. return 0;
  632. }
  633. #ifdef CONFIG_BOARD_LATE_INIT
  634. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  635. static int device_okay(const char *path)
  636. {
  637. int node;
  638. node = fdt_path_offset(gd->fdt_blob, path);
  639. if (node < 0)
  640. return 0;
  641. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  642. }
  643. #endif
  644. int board_late_init(void)
  645. {
  646. struct udevice *dev;
  647. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  648. set_board_info_env(NULL);
  649. /*
  650. * Default FIT boot on HS devices. Non FIT images are not allowed
  651. * on HS devices.
  652. */
  653. if (get_device_type() == HS_DEVICE)
  654. env_set("boot_fit", "1");
  655. #endif
  656. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  657. if (device_okay("/ocp/omap_dwc3@48380000"))
  658. enable_usb_clocks(0);
  659. if (device_okay("/ocp/omap_dwc3@483c0000"))
  660. enable_usb_clocks(1);
  661. #endif
  662. /* Just probe the potentially supported cdce913 device */
  663. uclass_get_device(UCLASS_CLK, 0, &dev);
  664. return 0;
  665. }
  666. #endif
  667. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  668. #ifdef CONFIG_USB_DWC3
  669. static struct dwc3_device usb_otg_ss1 = {
  670. .maximum_speed = USB_SPEED_HIGH,
  671. .base = USB_OTG_SS1_BASE,
  672. .tx_fifo_resize = false,
  673. .index = 0,
  674. };
  675. static struct dwc3_omap_device usb_otg_ss1_glue = {
  676. .base = (void *)USB_OTG_SS1_GLUE_BASE,
  677. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  678. .index = 0,
  679. };
  680. static struct ti_usb_phy_device usb_phy1_device = {
  681. .usb2_phy_power = (void *)USB2_PHY1_POWER,
  682. .index = 0,
  683. };
  684. static struct dwc3_device usb_otg_ss2 = {
  685. .maximum_speed = USB_SPEED_HIGH,
  686. .base = USB_OTG_SS2_BASE,
  687. .tx_fifo_resize = false,
  688. .index = 1,
  689. };
  690. static struct dwc3_omap_device usb_otg_ss2_glue = {
  691. .base = (void *)USB_OTG_SS2_GLUE_BASE,
  692. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  693. .index = 1,
  694. };
  695. static struct ti_usb_phy_device usb_phy2_device = {
  696. .usb2_phy_power = (void *)USB2_PHY2_POWER,
  697. .index = 1,
  698. };
  699. int usb_gadget_handle_interrupts(int index)
  700. {
  701. u32 status;
  702. status = dwc3_omap_uboot_interrupt_status(index);
  703. if (status)
  704. dwc3_uboot_handle_interrupt(index);
  705. return 0;
  706. }
  707. #endif /* CONFIG_USB_DWC3 */
  708. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  709. int board_usb_init(int index, enum usb_init_type init)
  710. {
  711. enable_usb_clocks(index);
  712. #ifdef CONFIG_USB_DWC3
  713. switch (index) {
  714. case 0:
  715. if (init == USB_INIT_DEVICE) {
  716. usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
  717. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  718. dwc3_omap_uboot_init(&usb_otg_ss1_glue);
  719. ti_usb_phy_uboot_init(&usb_phy1_device);
  720. dwc3_uboot_init(&usb_otg_ss1);
  721. }
  722. break;
  723. case 1:
  724. if (init == USB_INIT_DEVICE) {
  725. usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
  726. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  727. ti_usb_phy_uboot_init(&usb_phy2_device);
  728. dwc3_omap_uboot_init(&usb_otg_ss2_glue);
  729. dwc3_uboot_init(&usb_otg_ss2);
  730. }
  731. break;
  732. default:
  733. printf("Invalid Controller Index\n");
  734. }
  735. #endif
  736. return 0;
  737. }
  738. int board_usb_cleanup(int index, enum usb_init_type init)
  739. {
  740. #ifdef CONFIG_USB_DWC3
  741. switch (index) {
  742. case 0:
  743. case 1:
  744. if (init == USB_INIT_DEVICE) {
  745. ti_usb_phy_uboot_exit(index);
  746. dwc3_uboot_exit(index);
  747. dwc3_omap_uboot_exit(index);
  748. }
  749. break;
  750. default:
  751. printf("Invalid Controller Index\n");
  752. }
  753. #endif
  754. disable_usb_clocks(index);
  755. return 0;
  756. }
  757. #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
  758. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  759. #ifdef CONFIG_DRIVER_TI_CPSW
  760. static void cpsw_control(int enabled)
  761. {
  762. /* Additional controls can be added here */
  763. return;
  764. }
  765. static struct cpsw_slave_data cpsw_slaves[] = {
  766. {
  767. .slave_reg_ofs = 0x208,
  768. .sliver_reg_ofs = 0xd80,
  769. .phy_addr = 16,
  770. },
  771. {
  772. .slave_reg_ofs = 0x308,
  773. .sliver_reg_ofs = 0xdc0,
  774. .phy_addr = 1,
  775. },
  776. };
  777. static struct cpsw_platform_data cpsw_data = {
  778. .mdio_base = CPSW_MDIO_BASE,
  779. .cpsw_base = CPSW_BASE,
  780. .mdio_div = 0xff,
  781. .channels = 8,
  782. .cpdma_reg_ofs = 0x800,
  783. .slaves = 1,
  784. .slave_data = cpsw_slaves,
  785. .ale_reg_ofs = 0xd00,
  786. .ale_entries = 1024,
  787. .host_port_reg_ofs = 0x108,
  788. .hw_stats_reg_ofs = 0x900,
  789. .bd_ram_ofs = 0x2000,
  790. .mac_control = (1 << 5),
  791. .control = cpsw_control,
  792. .host_port_num = 0,
  793. .version = CPSW_CTRL_VERSION_2,
  794. };
  795. int board_eth_init(bd_t *bis)
  796. {
  797. int rv;
  798. uint8_t mac_addr[6];
  799. uint32_t mac_hi, mac_lo;
  800. /* try reading mac address from efuse */
  801. mac_lo = readl(&cdev->macid0l);
  802. mac_hi = readl(&cdev->macid0h);
  803. mac_addr[0] = mac_hi & 0xFF;
  804. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  805. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  806. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  807. mac_addr[4] = mac_lo & 0xFF;
  808. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  809. if (!env_get("ethaddr")) {
  810. puts("<ethaddr> not set. Validating first E-fuse MAC\n");
  811. if (is_valid_ethaddr(mac_addr))
  812. eth_env_set_enetaddr("ethaddr", mac_addr);
  813. }
  814. mac_lo = readl(&cdev->macid1l);
  815. mac_hi = readl(&cdev->macid1h);
  816. mac_addr[0] = mac_hi & 0xFF;
  817. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  818. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  819. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  820. mac_addr[4] = mac_lo & 0xFF;
  821. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  822. if (!env_get("eth1addr")) {
  823. if (is_valid_ethaddr(mac_addr))
  824. eth_env_set_enetaddr("eth1addr", mac_addr);
  825. }
  826. if (board_is_eposevm()) {
  827. writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
  828. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
  829. cpsw_slaves[0].phy_addr = 16;
  830. } else if (board_is_sk()) {
  831. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  832. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  833. cpsw_slaves[0].phy_addr = 4;
  834. cpsw_slaves[1].phy_addr = 5;
  835. } else if (board_is_idk()) {
  836. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  837. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  838. cpsw_slaves[0].phy_addr = 0;
  839. } else {
  840. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  841. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  842. cpsw_slaves[0].phy_addr = 0;
  843. }
  844. rv = cpsw_register(&cpsw_data);
  845. if (rv < 0)
  846. printf("Error %d registering CPSW switch\n", rv);
  847. return rv;
  848. }
  849. #endif
  850. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  851. int ft_board_setup(void *blob, bd_t *bd)
  852. {
  853. ft_cpu_setup(blob, bd);
  854. return 0;
  855. }
  856. #endif
  857. #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
  858. int board_fit_config_name_match(const char *name)
  859. {
  860. bool eeprom_read = board_ti_was_eeprom_read();
  861. if (!strcmp(name, "am4372-generic") && !eeprom_read)
  862. return 0;
  863. else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
  864. return 0;
  865. else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
  866. return 0;
  867. else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
  868. return 0;
  869. else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
  870. return 0;
  871. else
  872. return -1;
  873. }
  874. #endif
  875. #ifdef CONFIG_DTB_RESELECT
  876. int embedded_dtb_select(void)
  877. {
  878. do_board_detect();
  879. fdtdec_setup();
  880. return 0;
  881. }
  882. #endif
  883. #ifdef CONFIG_TI_SECURE_DEVICE
  884. void board_fit_image_post_process(void **p_image, size_t *p_size)
  885. {
  886. secure_boot_verify_image(p_image, p_size);
  887. }
  888. void board_tee_image_process(ulong tee_image, size_t tee_size)
  889. {
  890. secure_tee_install((u32)tee_image);
  891. }
  892. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  893. #endif