kmp204x.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <env.h>
  11. #include <fdt_support.h>
  12. #include <init.h>
  13. #include <netdev.h>
  14. #include <linux/compiler.h>
  15. #include <asm/mmu.h>
  16. #include <asm/processor.h>
  17. #include <asm/cache.h>
  18. #include <asm/immap_85xx.h>
  19. #include <asm/fsl_law.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <asm/fsl_portals.h>
  22. #include <asm/fsl_liodn.h>
  23. #include <fm_eth.h>
  24. #include "../common/common.h"
  25. #include "kmp204x.h"
  26. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  27. int checkboard(void)
  28. {
  29. printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
  30. return 0;
  31. }
  32. /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
  33. * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
  34. * For I2C only the low state is activly driven and high state is pulled-up
  35. * by a resistor. Therefore the deblock GPIOs are used
  36. * -> as an active output to drive a low state
  37. * -> as an open-drain input to have a pulled-up high state
  38. */
  39. /* QRIO GPIOs used for deblocking */
  40. #define DEBLOCK_PORT1 GPIO_A
  41. #define DEBLOCK_SCL1 20
  42. #define DEBLOCK_SDA1 21
  43. /* By default deblock GPIOs are floating */
  44. static void i2c_deblock_gpio_cfg(void)
  45. {
  46. /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
  47. qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
  48. qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
  49. qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
  50. qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
  51. }
  52. void set_sda(int state)
  53. {
  54. qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
  55. }
  56. void set_scl(int state)
  57. {
  58. qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
  59. }
  60. int get_sda(void)
  61. {
  62. return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
  63. }
  64. int get_scl(void)
  65. {
  66. return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
  67. }
  68. #define ZL30158_RST 8
  69. #define BFTIC4_RST 0
  70. #define RSTRQSR1_WDT_RR 0x00200000
  71. #define RSTRQSR1_SW_RR 0x00100000
  72. int board_early_init_f(void)
  73. {
  74. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  75. bool cpuwd_flag = false;
  76. /* configure mode for uP reset request */
  77. qrio_uprstreq(UPREQ_CORE_RST);
  78. /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
  79. setbits_be32(&gur->ddrclkdr, 0x001f000f);
  80. /* set reset reason according CPU register */
  81. if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
  82. RSTRQSR1_WDT_RR)
  83. cpuwd_flag = true;
  84. qrio_cpuwd_flag(cpuwd_flag);
  85. /* clear CPU bits by writing 1 */
  86. setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
  87. /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
  88. qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
  89. /* and enable WD on it */
  90. qrio_wdmask(BFTIC4_RST, true);
  91. /* set the ZL30138's prstcfg to reset at power-up only */
  92. qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
  93. /* and take it out of reset as soon as possible (needed for Hooper) */
  94. qrio_prst(ZL30158_RST, false, false);
  95. return 0;
  96. }
  97. int board_early_init_r(void)
  98. {
  99. int ret = 0;
  100. /* Flush d-cache and invalidate i-cache of any FLASH data */
  101. flush_dcache();
  102. invalidate_icache();
  103. set_liodns();
  104. setup_qbman_portals();
  105. ret = trigger_fpga_config();
  106. if (ret)
  107. printf("error triggering PCIe FPGA config\n");
  108. /* enable the Unit LED (red) & Boot LED (on) */
  109. qrio_set_leds();
  110. /* enable Application Buffer */
  111. qrio_enable_app_buffer();
  112. return ret;
  113. }
  114. unsigned long get_board_sys_clk(unsigned long dummy)
  115. {
  116. return 66666666;
  117. }
  118. #define ETH_FRONT_PHY_RST 15
  119. #define QSFP2_RST 11
  120. #define QSFP1_RST 10
  121. #define ZL30343_RST 9
  122. int misc_init_f(void)
  123. {
  124. /* configure QRIO pis for i2c deblocking */
  125. i2c_deblock_gpio_cfg();
  126. /* configure the front phy's prstcfg and take it out of reset */
  127. qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  128. qrio_prst(ETH_FRONT_PHY_RST, false, false);
  129. /* set the ZL30343 prstcfg to reset at power-up only */
  130. qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
  131. /* and enable the WD on it */
  132. qrio_wdmask(ZL30343_RST, true);
  133. /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
  134. qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
  135. qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
  136. /* and enable the WD on them */
  137. qrio_wdmask(QSFP1_RST, true);
  138. qrio_wdmask(QSFP2_RST, true);
  139. return 0;
  140. }
  141. #define NUM_SRDS_BANKS 2
  142. int misc_init_r(void)
  143. {
  144. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  145. u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
  146. SRDS_PLLCR0_RFCK_SEL_125};
  147. unsigned int i;
  148. /* check SERDES reference clocks */
  149. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  150. u32 actual = in_be32(&regs->bank[i].pllcr0);
  151. actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
  152. if (actual != expected[i]) {
  153. printf("Warning: SERDES bank %u expects reference \
  154. clock %sMHz, but actual is %sMHz\n", i + 1,
  155. serdes_clock_to_string(expected[i]),
  156. serdes_clock_to_string(actual));
  157. }
  158. }
  159. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  160. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  161. return 0;
  162. }
  163. #if defined(CONFIG_HUSH_INIT_VAR)
  164. int hush_init_var(void)
  165. {
  166. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  167. return 0;
  168. }
  169. #endif
  170. #if defined(CONFIG_LAST_STAGE_INIT)
  171. int last_stage_init(void)
  172. {
  173. #if defined(CONFIG_KMCOGE4)
  174. /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
  175. struct bfticu_iomap *bftic4 =
  176. (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
  177. u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
  178. if (dip_switch != 0) {
  179. /* start bootloader */
  180. puts("DIP: Enabled\n");
  181. env_set("actual_bank", "0");
  182. }
  183. #endif
  184. set_km_env();
  185. return 0;
  186. }
  187. #endif
  188. #ifdef CONFIG_SYS_DPAA_FMAN
  189. void fdt_fixup_fman_mac_addresses(void *blob)
  190. {
  191. int node, i, ret;
  192. char *tmp, *end;
  193. unsigned char mac_addr[6];
  194. /* get the mac addr from env */
  195. tmp = env_get("ethaddr");
  196. if (!tmp) {
  197. printf("ethaddr env variable not defined\n");
  198. return;
  199. }
  200. for (i = 0; i < 6; i++) {
  201. mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
  202. if (tmp)
  203. tmp = (*end) ? end+1 : end;
  204. }
  205. /* find the correct fdt ethernet path and correct it */
  206. node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
  207. if (node < 0) {
  208. printf("no /soc/fman/ethernet path offset\n");
  209. return;
  210. }
  211. ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
  212. if (ret) {
  213. printf("error setting local-mac-address property\n");
  214. return;
  215. }
  216. }
  217. #endif
  218. int ft_board_setup(void *blob, bd_t *bd)
  219. {
  220. phys_addr_t base;
  221. phys_size_t size;
  222. ft_cpu_setup(blob, bd);
  223. base = env_get_bootm_low();
  224. size = env_get_bootm_size();
  225. fdt_fixup_memory(blob, (u64)base, (u64)size);
  226. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  227. fsl_fdt_fixup_dr_usb(blob, bd);
  228. #endif
  229. #ifdef CONFIG_PCI
  230. pci_of_setup(blob, bd);
  231. #endif
  232. fdt_fixup_liodn(blob);
  233. #ifdef CONFIG_SYS_DPAA_FMAN
  234. fdt_fixup_fman_ethernet(blob);
  235. fdt_fixup_fman_mac_addresses(blob);
  236. #endif
  237. return 0;
  238. }
  239. #if defined(CONFIG_POST)
  240. /* DIC26_SELFTEST GPIO used to start factory test sw */
  241. #define SELFTEST_PORT GPIO_A
  242. #define SELFTEST_PIN 31
  243. int post_hotkeys_pressed(void)
  244. {
  245. qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
  246. return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
  247. }
  248. #endif