ids8313.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (c) 2011 IDS GmbH, Germany
  8. * ids8313.c - ids8313 board support.
  9. *
  10. * Sergej Stepanov <ste@ids.de>
  11. * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
  12. */
  13. #include <common.h>
  14. #include <fdt_support.h>
  15. #include <mpc83xx.h>
  16. #include <spi.h>
  17. #include <linux/libfdt.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /** CPLD contains the info about:
  20. * - board type: *pCpld & 0xF0
  21. * - hw-revision: *pCpld & 0x0F
  22. * - cpld-revision: *pCpld+1
  23. */
  24. int checkboard(void)
  25. {
  26. char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
  27. u8 u8Vers = readb(pcpld);
  28. u8 u8Revs = readb(pcpld + 1);
  29. printf("Board: ");
  30. switch (u8Vers & 0xF0) {
  31. case '\x40':
  32. printf("CU73X");
  33. break;
  34. case '\x50':
  35. printf("CC73X");
  36. break;
  37. default:
  38. printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
  39. return 0;
  40. }
  41. printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
  42. u8Vers & 0x0F, u8Revs & 0xFF);
  43. return 0;
  44. }
  45. /*
  46. * fixed sdram init
  47. */
  48. int fixed_sdram(unsigned long config)
  49. {
  50. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  51. u32 msize = CONFIG_SYS_DDR_SIZE << 20;
  52. #ifndef CONFIG_SYS_RAMBOOT
  53. u32 msize_log2 = __ilog2(msize);
  54. out_be32(&im->sysconf.ddrlaw[0].bar,
  55. (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
  56. out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
  57. out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  58. sync();
  59. /*
  60. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  61. * or the DDR2 controller may fail to initialize correctly.
  62. */
  63. udelay(50000);
  64. out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
  65. out_be32(&im->ddr.cs_config[0], config);
  66. /* currently we use only one CS, so disable the other banks */
  67. out_be32(&im->ddr.cs_config[1], 0);
  68. out_be32(&im->ddr.cs_config[2], 0);
  69. out_be32(&im->ddr.cs_config[3], 0);
  70. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  71. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  72. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  73. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  74. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
  75. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
  76. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  77. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
  78. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  79. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  80. sync();
  81. udelay(300);
  82. /* enable DDR controller */
  83. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  84. /* now check the real size */
  85. disable_addr_trans();
  86. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  87. enable_addr_trans();
  88. #endif
  89. return msize;
  90. }
  91. static int setup_sdram(void)
  92. {
  93. u32 msize = CONFIG_SYS_DDR_SIZE << 20;
  94. long int size_01, size_02;
  95. size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
  96. size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
  97. if (size_01 > size_02)
  98. msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
  99. else
  100. msize = size_02;
  101. return msize;
  102. }
  103. int dram_init(void)
  104. {
  105. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  106. fsl_lbc_t *lbc = &im->im_lbc;
  107. u32 msize = 0;
  108. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  109. return -ENXIO;
  110. msize = setup_sdram();
  111. out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
  112. out_be32(&lbc->mrtpr, 0x20000000);
  113. sync();
  114. gd->ram_size = msize;
  115. return 0;
  116. }
  117. #if defined(CONFIG_OF_BOARD_SETUP)
  118. int ft_board_setup(void *blob, bd_t *bd)
  119. {
  120. ft_cpu_setup(blob, bd);
  121. return 0;
  122. }
  123. #endif
  124. /* gpio mask for spi_cs */
  125. #define IDSCPLD_SPI_CS_MASK 0x00000001
  126. /* spi_cs multiplexed through cpld */
  127. #define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
  128. #if defined(CONFIG_MISC_INIT_R)
  129. /* srp umcr mask for rts */
  130. #define IDSUMCR_RTS_MASK 0x04
  131. int misc_init_r(void)
  132. {
  133. /*srp*/
  134. duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
  135. duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
  136. gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  137. u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  138. /* deactivate spi_cs channels */
  139. out_8(spi_base, 0);
  140. /* deactivate the spi_cs */
  141. setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
  142. /*srp - deactivate rts*/
  143. out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
  144. out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
  145. gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
  146. return 0;
  147. }
  148. #endif
  149. #ifdef CONFIG_MPC8XXX_SPI
  150. /*
  151. * The following are used to control the SPI chip selects
  152. */
  153. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  154. {
  155. return bus == 0 && ((cs >= 0) && (cs <= 2));
  156. }
  157. void spi_cs_activate(struct spi_slave *slave)
  158. {
  159. gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  160. u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  161. /* select the spi_cs channel */
  162. out_8(spi_base, 1 << slave->cs);
  163. /* activate the spi_cs */
  164. clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
  165. }
  166. void spi_cs_deactivate(struct spi_slave *slave)
  167. {
  168. gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  169. u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
  170. /* select the spi_cs channel */
  171. out_8(spi_base, 1 << slave->cs);
  172. /* deactivate the spi_cs */
  173. setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
  174. }
  175. #endif