t208xqds.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <fm_eth.h>
  20. #include "../common/qixis.h"
  21. #include "../common/vsc3316_3308.h"
  22. #include "../common/vid.h"
  23. #include "t208xqds.h"
  24. #include "t208xqds_qixis.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. int checkboard(void)
  27. {
  28. char buf[64];
  29. u8 sw;
  30. struct cpu_type *cpu = gd->arch.cpu;
  31. static const char *freq[4] = {
  32. "100.00MHZ(from 8T49N222A)", "125.00MHz",
  33. "156.25MHZ", "100.00MHz"
  34. };
  35. printf("Board: %sQDS, ", cpu->name);
  36. sw = QIXIS_READ(arch);
  37. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  38. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  39. #ifdef CONFIG_SDCARD
  40. puts("SD/MMC\n");
  41. #elif CONFIG_SPIFLASH
  42. puts("SPI\n");
  43. #else
  44. sw = QIXIS_READ(brdcfg[0]);
  45. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  46. if (sw < 0x8)
  47. printf("vBank%d\n", sw);
  48. else if (sw == 0x8)
  49. puts("Promjet\n");
  50. else if (sw == 0x9)
  51. puts("NAND\n");
  52. else
  53. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  54. #endif
  55. printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  56. qixis_read_tag(buf), (int)qixis_read_minor());
  57. /* the timestamp string contains "\n" at the end */
  58. printf(" on %s", qixis_read_time(buf));
  59. puts("SERDES Reference Clocks:\n");
  60. sw = QIXIS_READ(brdcfg[2]);
  61. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  62. freq[(sw >> 4) & 0x3]);
  63. printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  64. freq[sw & 0x3]);
  65. return 0;
  66. }
  67. int select_i2c_ch_pca9547(u8 ch)
  68. {
  69. int ret;
  70. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  71. if (ret) {
  72. puts("PCA: failed to select proper channel\n");
  73. return ret;
  74. }
  75. return 0;
  76. }
  77. int i2c_multiplexer_select_vid_channel(u8 channel)
  78. {
  79. return select_i2c_ch_pca9547(channel);
  80. }
  81. int brd_mux_lane_to_slot(void)
  82. {
  83. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  84. u32 srds_prtcl_s1;
  85. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  86. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  87. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  88. #if defined(CONFIG_TARGET_T2080QDS)
  89. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  90. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  91. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  92. #endif
  93. switch (srds_prtcl_s1) {
  94. case 0:
  95. /* SerDes1 is not enabled */
  96. break;
  97. #if defined(CONFIG_TARGET_T2080QDS)
  98. case 0x1b:
  99. case 0x1c:
  100. case 0xa2:
  101. /* SD1(A:D) => SLOT3 SGMII
  102. * SD1(G:H) => SLOT1 SGMII
  103. */
  104. QIXIS_WRITE(brdcfg[12], 0x1a);
  105. break;
  106. case 0x94:
  107. case 0x95:
  108. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  109. * SD1(C:D) => SFP Module, SGMII@3.125bps
  110. * SD1(E:H) => SLOT1 SGMII@1.25bps
  111. */
  112. case 0x96:
  113. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  114. * SD1(C) => SFP Module, SGMII@3.125bps
  115. * SD1(D) => SFP Module, SGMII@1.25bps
  116. * SD1(E:H) => SLOT1 PCIe4 x4
  117. */
  118. QIXIS_WRITE(brdcfg[12], 0x3a);
  119. break;
  120. case 0x50:
  121. case 0x51:
  122. /* SD1(A:D) => SLOT3 XAUI
  123. * SD1(E) => SLOT1 PCIe4
  124. * SD1(F:H) => SLOT2 SGMII
  125. */
  126. QIXIS_WRITE(brdcfg[12], 0x15);
  127. break;
  128. case 0x66:
  129. case 0x67:
  130. /* SD1(A:D) => XFI cage
  131. * SD1(E:H) => SLOT1 PCIe4
  132. */
  133. QIXIS_WRITE(brdcfg[12], 0xfe);
  134. break;
  135. case 0x6a:
  136. case 0x6b:
  137. /* SD1(A:D) => XFI cage
  138. * SD1(E) => SLOT1 PCIe4
  139. * SD1(F:H) => SLOT2 SGMII
  140. */
  141. QIXIS_WRITE(brdcfg[12], 0xf1);
  142. break;
  143. case 0x6c:
  144. case 0x6d:
  145. /* SD1(A:B) => XFI cage
  146. * SD1(C:D) => SLOT3 SGMII
  147. * SD1(E:H) => SLOT1 PCIe4
  148. */
  149. QIXIS_WRITE(brdcfg[12], 0xda);
  150. break;
  151. case 0x6e:
  152. /* SD1(A:B) => SFP Module, XFI
  153. * SD1(C:D) => SLOT3 SGMII
  154. * SD1(E:F) => SLOT1 PCIe4 x2
  155. * SD1(G:H) => SLOT2 SGMII
  156. */
  157. QIXIS_WRITE(brdcfg[12], 0xd9);
  158. break;
  159. case 0xda:
  160. /* SD1(A:H) => SLOT3 PCIe3 x8
  161. */
  162. QIXIS_WRITE(brdcfg[12], 0x0);
  163. break;
  164. case 0xc8:
  165. /* SD1(A) => SLOT3 PCIe3 x1
  166. * SD1(B) => SFP Module, SGMII@1.25bps
  167. * SD1(C:D) => SFP Module, SGMII@3.125bps
  168. * SD1(E:F) => SLOT1 PCIe4 x2
  169. * SD1(G:H) => SLOT2 SGMII
  170. */
  171. QIXIS_WRITE(brdcfg[12], 0x79);
  172. break;
  173. case 0xab:
  174. /* SD1(A:D) => SLOT3 PCIe3 x4
  175. * SD1(E:H) => SLOT1 PCIe4 x4
  176. */
  177. QIXIS_WRITE(brdcfg[12], 0x1a);
  178. break;
  179. #elif defined(CONFIG_TARGET_T2081QDS)
  180. case 0x50:
  181. case 0x51:
  182. /* SD1(A:D) => SLOT2 XAUI
  183. * SD1(E) => SLOT1 PCIe4 x1
  184. * SD1(F:H) => SLOT3 SGMII
  185. */
  186. QIXIS_WRITE(brdcfg[12], 0x98);
  187. QIXIS_WRITE(brdcfg[13], 0x70);
  188. break;
  189. case 0x6a:
  190. case 0x6b:
  191. /* SD1(A:D) => XFI SFP Module
  192. * SD1(E) => SLOT1 PCIe4 x1
  193. * SD1(F:H) => SLOT3 SGMII
  194. */
  195. QIXIS_WRITE(brdcfg[12], 0x80);
  196. QIXIS_WRITE(brdcfg[13], 0x70);
  197. break;
  198. case 0x6c:
  199. case 0x6d:
  200. /* SD1(A:B) => XFI SFP Module
  201. * SD1(C:D) => SLOT2 SGMII
  202. * SD1(E:H) => SLOT1 PCIe4 x4
  203. */
  204. QIXIS_WRITE(brdcfg[12], 0xe8);
  205. QIXIS_WRITE(brdcfg[13], 0x0);
  206. break;
  207. case 0xaa:
  208. case 0xab:
  209. /* SD1(A:D) => SLOT2 PCIe3 x4
  210. * SD1(F:H) => SLOT1 SGMI4 x4
  211. */
  212. QIXIS_WRITE(brdcfg[12], 0xf8);
  213. QIXIS_WRITE(brdcfg[13], 0x0);
  214. break;
  215. case 0xca:
  216. case 0xcb:
  217. /* SD1(A) => SLOT2 PCIe3 x1
  218. * SD1(B) => SLOT7 SGMII
  219. * SD1(C) => SLOT6 SGMII
  220. * SD1(D) => SLOT5 SGMII
  221. * SD1(E) => SLOT1 PCIe4 x1
  222. * SD1(F:H) => SLOT3 SGMII
  223. */
  224. QIXIS_WRITE(brdcfg[12], 0x80);
  225. QIXIS_WRITE(brdcfg[13], 0x70);
  226. break;
  227. case 0xde:
  228. case 0xdf:
  229. /* SD1(A:D) => SLOT2 PCIe3 x4
  230. * SD1(E) => SLOT1 PCIe4 x1
  231. * SD1(F) => SLOT4 PCIe1 x1
  232. * SD1(G) => SLOT3 PCIe2 x1
  233. * SD1(H) => SLOT7 SGMII
  234. */
  235. QIXIS_WRITE(brdcfg[12], 0x98);
  236. QIXIS_WRITE(brdcfg[13], 0x25);
  237. break;
  238. case 0xf2:
  239. /* SD1(A) => SLOT2 PCIe3 x1
  240. * SD1(B:D) => SLOT7 SGMII
  241. * SD1(E) => SLOT1 PCIe4 x1
  242. * SD1(F) => SLOT4 PCIe1 x1
  243. * SD1(G) => SLOT3 PCIe2 x1
  244. * SD1(H) => SLOT7 SGMII
  245. */
  246. QIXIS_WRITE(brdcfg[12], 0x81);
  247. QIXIS_WRITE(brdcfg[13], 0xa5);
  248. break;
  249. #endif
  250. default:
  251. printf("WARNING: unsupported for SerDes1 Protocol %d\n",
  252. srds_prtcl_s1);
  253. return -1;
  254. }
  255. #ifdef CONFIG_TARGET_T2080QDS
  256. switch (srds_prtcl_s2) {
  257. case 0:
  258. /* SerDes2 is not enabled */
  259. break;
  260. case 0x01:
  261. case 0x02:
  262. /* SD2(A:H) => SLOT4 PCIe1 */
  263. QIXIS_WRITE(brdcfg[13], 0x10);
  264. break;
  265. case 0x15:
  266. case 0x16:
  267. /*
  268. * SD2(A:D) => SLOT4 PCIe1
  269. * SD2(E:F) => SLOT5 PCIe2
  270. * SD2(G:H) => SATA1,SATA2
  271. */
  272. QIXIS_WRITE(brdcfg[13], 0xb0);
  273. break;
  274. case 0x18:
  275. /*
  276. * SD2(A:D) => SLOT4 PCIe1
  277. * SD2(E:F) => SLOT5 Aurora
  278. * SD2(G:H) => SATA1,SATA2
  279. */
  280. QIXIS_WRITE(brdcfg[13], 0x78);
  281. break;
  282. case 0x1f:
  283. /*
  284. * SD2(A:D) => SLOT4 PCIe1
  285. * SD2(E:H) => SLOT5 PCIe2
  286. */
  287. QIXIS_WRITE(brdcfg[13], 0xa0);
  288. break;
  289. case 0x29:
  290. case 0x2d:
  291. case 0x2e:
  292. /*
  293. * SD2(A:D) => SLOT4 SRIO2
  294. * SD2(E:H) => SLOT5 SRIO1
  295. */
  296. QIXIS_WRITE(brdcfg[13], 0xa0);
  297. break;
  298. case 0x36:
  299. /*
  300. * SD2(A:D) => SLOT4 SRIO2
  301. * SD2(E:F) => Aurora
  302. * SD2(G:H) => SATA1,SATA2
  303. */
  304. QIXIS_WRITE(brdcfg[13], 0x78);
  305. break;
  306. default:
  307. printf("WARNING: unsupported for SerDes2 Protocol %d\n",
  308. srds_prtcl_s2);
  309. return -1;
  310. }
  311. #endif
  312. return 0;
  313. }
  314. int board_early_init_r(void)
  315. {
  316. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  317. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  318. /*
  319. * Remap Boot flash + PROMJET region to caching-inhibited
  320. * so that flash can be erased properly.
  321. */
  322. /* Flush d-cache and invalidate i-cache of any FLASH data */
  323. flush_dcache();
  324. invalidate_icache();
  325. if (flash_esel == -1) {
  326. /* very unlikely unless something is messed up */
  327. puts("Error: Could not find TLB for FLASH BASE\n");
  328. flash_esel = 2; /* give our best effort to continue */
  329. } else {
  330. /* invalidate existing TLB entry for flash + promjet */
  331. disable_tlb(flash_esel);
  332. }
  333. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  334. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  335. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  336. /* Disable remote I2C connection to qixis fpga */
  337. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  338. /*
  339. * Adjust core voltage according to voltage ID
  340. * This function changes I2C mux to channel 2.
  341. */
  342. if (adjust_vdd(0))
  343. printf("Warning: Adjusting core voltage failed.\n");
  344. brd_mux_lane_to_slot();
  345. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  346. return 0;
  347. }
  348. unsigned long get_board_sys_clk(void)
  349. {
  350. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  351. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  352. /* use accurate clock measurement */
  353. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  354. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  355. u32 val;
  356. val = freq * base;
  357. if (val) {
  358. debug("SYS Clock measurement is: %d\n", val);
  359. return val;
  360. } else {
  361. printf("Warning: SYS clock measurement is invalid, ");
  362. printf("using value from brdcfg1.\n");
  363. }
  364. #endif
  365. switch (sysclk_conf & 0x0F) {
  366. case QIXIS_SYSCLK_83:
  367. return 83333333;
  368. case QIXIS_SYSCLK_100:
  369. return 100000000;
  370. case QIXIS_SYSCLK_125:
  371. return 125000000;
  372. case QIXIS_SYSCLK_133:
  373. return 133333333;
  374. case QIXIS_SYSCLK_150:
  375. return 150000000;
  376. case QIXIS_SYSCLK_160:
  377. return 160000000;
  378. case QIXIS_SYSCLK_166:
  379. return 166666666;
  380. }
  381. return 66666666;
  382. }
  383. unsigned long get_board_ddr_clk(void)
  384. {
  385. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  386. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  387. /* use accurate clock measurement */
  388. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  389. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  390. u32 val;
  391. val = freq * base;
  392. if (val) {
  393. debug("DDR Clock measurement is: %d\n", val);
  394. return val;
  395. } else {
  396. printf("Warning: DDR clock measurement is invalid, ");
  397. printf("using value from brdcfg1.\n");
  398. }
  399. #endif
  400. switch ((ddrclk_conf & 0x30) >> 4) {
  401. case QIXIS_DDRCLK_100:
  402. return 100000000;
  403. case QIXIS_DDRCLK_125:
  404. return 125000000;
  405. case QIXIS_DDRCLK_133:
  406. return 133333333;
  407. }
  408. return 66666666;
  409. }
  410. int misc_init_r(void)
  411. {
  412. return 0;
  413. }
  414. int ft_board_setup(void *blob, bd_t *bd)
  415. {
  416. phys_addr_t base;
  417. phys_size_t size;
  418. ft_cpu_setup(blob, bd);
  419. base = env_get_bootm_low();
  420. size = env_get_bootm_size();
  421. fdt_fixup_memory(blob, (u64)base, (u64)size);
  422. #ifdef CONFIG_PCI
  423. pci_of_setup(blob, bd);
  424. #endif
  425. fdt_fixup_liodn(blob);
  426. fsl_fdt_fixup_dr_usb(blob, bd);
  427. #ifdef CONFIG_SYS_DPAA_FMAN
  428. fdt_fixup_fman_ethernet(blob);
  429. fdt_fixup_board_enet(blob);
  430. #endif
  431. return 0;
  432. }