t1040qds.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. #include <hwconfig.h>
  22. #include "../common/sleep.h"
  23. #include "../common/qixis.h"
  24. #include "t1040qds.h"
  25. #include "t1040qds_qixis.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. int checkboard(void)
  28. {
  29. char buf[64];
  30. u8 sw;
  31. struct cpu_type *cpu = gd->arch.cpu;
  32. static const char *const freq[] = {"100", "125", "156.25", "161.13",
  33. "122.88", "122.88", "122.88"};
  34. int clock;
  35. printf("Board: %sQDS, ", cpu->name);
  36. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  37. QIXIS_READ(id), QIXIS_READ(arch));
  38. sw = QIXIS_READ(brdcfg[0]);
  39. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  40. if (sw < 0x8)
  41. printf("vBank: %d\n", sw);
  42. else if (sw == 0x8)
  43. puts("PromJet\n");
  44. else if (sw == 0x9)
  45. puts("NAND\n");
  46. else if (sw == 0x15)
  47. printf("IFCCard\n");
  48. else
  49. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  50. printf("FPGA: v%d (%s), build %d",
  51. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  52. (int)qixis_read_minor());
  53. /* the timestamp string contains "\n" at the end */
  54. printf(" on %s", qixis_read_time(buf));
  55. /*
  56. * Display the actual SERDES reference clocks as configured by the
  57. * dip switches on the board. Note that the SWx registers could
  58. * technically be set to force the reference clocks to match the
  59. * values that the SERDES expects (or vice versa). For now, however,
  60. * we just display both values and hope the user notices when they
  61. * don't match.
  62. */
  63. puts("SERDES Reference: ");
  64. sw = QIXIS_READ(brdcfg[2]);
  65. clock = (sw >> 6) & 3;
  66. printf("Clock1=%sMHz ", freq[clock]);
  67. clock = (sw >> 4) & 3;
  68. printf("Clock2=%sMHz\n", freq[clock]);
  69. return 0;
  70. }
  71. int select_i2c_ch_pca9547(u8 ch)
  72. {
  73. int ret;
  74. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  75. if (ret) {
  76. puts("PCA: failed to select proper channel\n");
  77. return ret;
  78. }
  79. return 0;
  80. }
  81. static void qe_board_setup(void)
  82. {
  83. u8 brdcfg15, brdcfg9;
  84. if (hwconfig("qe") && hwconfig("tdm")) {
  85. brdcfg15 = QIXIS_READ(brdcfg[15]);
  86. /*
  87. * TDMRiser uses QE-TDM
  88. * Route QE_TDM signals to TDM Riser slot
  89. */
  90. QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
  91. } else if (hwconfig("qe") && hwconfig("uart")) {
  92. brdcfg15 = QIXIS_READ(brdcfg[15]);
  93. brdcfg9 = QIXIS_READ(brdcfg[9]);
  94. /*
  95. * Route QE_TDM signals to UCC
  96. * ProfiBus controlled by UCC3
  97. */
  98. brdcfg15 &= 0xfc;
  99. QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
  100. QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
  101. }
  102. }
  103. int board_early_init_f(void)
  104. {
  105. #if defined(CONFIG_DEEP_SLEEP)
  106. if (is_warm_boot())
  107. fsl_dp_disable_console();
  108. #endif
  109. return 0;
  110. }
  111. int board_early_init_r(void)
  112. {
  113. #ifdef CONFIG_SYS_FLASH_BASE
  114. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  115. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  116. /*
  117. * Remap Boot flash + PROMJET region to caching-inhibited
  118. * so that flash can be erased properly.
  119. */
  120. /* Flush d-cache and invalidate i-cache of any FLASH data */
  121. flush_dcache();
  122. invalidate_icache();
  123. if (flash_esel == -1) {
  124. /* very unlikely unless something is messed up */
  125. puts("Error: Could not find TLB for FLASH BASE\n");
  126. flash_esel = 2; /* give our best effort to continue */
  127. } else {
  128. /* invalidate existing TLB entry for flash + promjet */
  129. disable_tlb(flash_esel);
  130. }
  131. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  132. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  133. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  134. #endif
  135. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  136. return 0;
  137. }
  138. unsigned long get_board_sys_clk(void)
  139. {
  140. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  141. switch (sysclk_conf & 0x0F) {
  142. case QIXIS_SYSCLK_64:
  143. return 64000000;
  144. case QIXIS_SYSCLK_83:
  145. return 83333333;
  146. case QIXIS_SYSCLK_100:
  147. return 100000000;
  148. case QIXIS_SYSCLK_125:
  149. return 125000000;
  150. case QIXIS_SYSCLK_133:
  151. return 133333333;
  152. case QIXIS_SYSCLK_150:
  153. return 150000000;
  154. case QIXIS_SYSCLK_160:
  155. return 160000000;
  156. case QIXIS_SYSCLK_166:
  157. return 166666666;
  158. }
  159. return 66666666;
  160. }
  161. unsigned long get_board_ddr_clk(void)
  162. {
  163. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  164. switch ((ddrclk_conf & 0x30) >> 4) {
  165. case QIXIS_DDRCLK_100:
  166. return 100000000;
  167. case QIXIS_DDRCLK_125:
  168. return 125000000;
  169. case QIXIS_DDRCLK_133:
  170. return 133333333;
  171. }
  172. return 66666666;
  173. }
  174. #define NUM_SRDS_BANKS 2
  175. int misc_init_r(void)
  176. {
  177. u8 sw;
  178. serdes_corenet_t *srds_regs =
  179. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  180. u32 actual[NUM_SRDS_BANKS] = { 0 };
  181. int i;
  182. sw = QIXIS_READ(brdcfg[2]);
  183. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  184. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  185. switch (clock) {
  186. case 0:
  187. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  188. break;
  189. case 1:
  190. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  191. break;
  192. case 2:
  193. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  194. break;
  195. }
  196. }
  197. puts("SerDes1");
  198. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  199. u32 pllcr0 = srds_regs->bank[i].pllcr0;
  200. u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  201. if (expected != actual[i]) {
  202. printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
  203. i + 1, serdes_clock_to_string(expected),
  204. serdes_clock_to_string(actual[i]));
  205. }
  206. }
  207. qe_board_setup();
  208. return 0;
  209. }
  210. int ft_board_setup(void *blob, bd_t *bd)
  211. {
  212. phys_addr_t base;
  213. phys_size_t size;
  214. ft_cpu_setup(blob, bd);
  215. base = env_get_bootm_low();
  216. size = env_get_bootm_size();
  217. fdt_fixup_memory(blob, (u64)base, (u64)size);
  218. #ifdef CONFIG_PCI
  219. pci_of_setup(blob, bd);
  220. #endif
  221. fdt_fixup_liodn(blob);
  222. #ifdef CONFIG_HAS_FSL_DR_USB
  223. fsl_fdt_fixup_dr_usb(blob, bd);
  224. #endif
  225. #ifdef CONFIG_SYS_DPAA_FMAN
  226. fdt_fixup_fman_ethernet(blob);
  227. fdt_fixup_board_enet(blob);
  228. #endif
  229. return 0;
  230. }
  231. void qixis_dump_switch(void)
  232. {
  233. int i, nr_of_cfgsw;
  234. QIXIS_WRITE(cms[0], 0x00);
  235. nr_of_cfgsw = QIXIS_READ(cms[1]);
  236. puts("DIP switch settings dump:\n");
  237. for (i = 1; i <= nr_of_cfgsw; i++) {
  238. QIXIS_WRITE(cms[0], i);
  239. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  240. }
  241. }
  242. int board_need_mem_reset(void)
  243. {
  244. return 1;
  245. }